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 What Would Joe Do?

Archive for May, 2012

Kathryn Kranen: the paradigm shifts at EDAC

Thursday, May 31st, 2012

 

Stop the presses! Someone other than the CEO of Mentor, Synopsys, or Cadence is going to be the Chair of EDAC.

What? Has the world come to an end?

Nope, but it turns out that even staid EDAC has, at last, learned how to innovate. It turns out that Mentor, Synopsys, and Cadence have, at least, seen the light and decided that they shouldn’t always be at the head of the class. As of yesterday, May 31st, there’s a new Chair at EDAC and it’s Kathryn Kranen, President & CEO at Jasper Design Automation.

Kathryn, of course, is well known within the EDA community. She’s been CEO at Jasper since 2003. Prior to Jasper, Kathryn was CEO of Verisity Design, and earlier on served as VP of North American sales at Quickturn. At the outset of her career, after earning a BSEE at Texas A&M, she worked as a design engineer at Rockwell, and then joined Daisy Systems in advance of her role at Quickturn.

In addition, Kathryn was named the 2005 recipient of the Marie R. Pistilli Woman in EDA Achievement Award, and has been an extremely hard working member of the Board of Directors of EDAC for many years.

I am personally elated at the news, and wish Kathryn all the best!

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Uniquify: The Vision is crystal clear

Thursday, May 31st, 2012

 

If Silicon Valley is all about articulating and executing on a vision, then Santa Clara based Uniquify is all about Silicon Valley. The company has been in business since 2005, and since that time has worked to crystallize and clarify its vision and road map.

The vision is succinct and to the point: Make creating chips easier and faster, and with better results.

And from what I heard on a lengthy phone call today with Uniquify CEO Josh Lee, the company thinks they’ve nailed it, realizing that vision in three distinct ways. Per Lee, “Number one is design services. With us this is a different beast than in the usual sense in that we start from a spec or idea from our customer, and take it all the way to GDS.

“In the past, design services – which emerged in the mid-1990s when the industry moved from the ASIC to the COT model – were either dealing with logical design or phsycial design. At Uniquify, however, we are doing them both together. As a result, our core business is best described as ‘from spec to GDS’.

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EVE: a question of Focus

Wednesday, May 30th, 2012

 

Founded in 2000 in France, EVE has been a highly visible part of the EDA landscape for over a decade. In the week prior to the Design Automation Conference in San Francisco, I spoke by phone with Lauro Rizatti, General Manager and Marketing VP for EVA-USA, headquartered in Silicon Valley.

Lauro said that EVE is not releasing specific news at DAC because the company is launching the newest version of its ZeBu emulator in November 2012, the ZeBu-Server2 based on the Xilinx Virtex 6. Following that, EVE will be releasing the ZeBu-Server3 in mid-2014 based on the newest version of Xilinx Virtex 7. It’s not a coincidence that EVE’s hardware, built around ‘off the shelf’ FPGAs, enjoys a new release every two years.

Per Lauro: “Working with FPGAs, we don’t have to wait for internal, custom chip development to move forward. And because we use Xilinx, we ride their technology road map. Every 2 years they launch a new platform, and every 2 years so does Eve. We think we have a brilliant strategy, and the results can be seen in our earnings. We recognized $52 million revenue and $62 million in bookings over the last 12 months.”

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Dr. Belle Wei: 2012 Marie R. Pistilli Achievement Award

Thursday, May 24th, 2012

 

At the center of the technical universe sits Silicon Valley. At the center of Silicon Valley sits the City of San Jose. At the center of the city sits San Jose State University, and at the center of the university sits the Charles W. Davidson College of Engineering.

Currently, SJSU offers 12 undergraduate majors in engineering, 11 graduate majors, and a host of different inter-disciplinary programs at all levels. It’s a dynamic College of Engineering and a powerful magnet for study in Northern California.

Dr. Belle Wei (M.S.E. Harvard, Ph.D. U.C. Berkeley) has been Dean of the College of Engineering since 2002, and is now serving a second 6-year term. On Monday, June 4th, at the Design Automation Conference in San Francisco, Dean Wei will receive the 2012 Marie R. Pistilli Achievement Award.

Per the press announcement of her Marie R. Pistilli award: “Dr. Wei is the first person in the College of  Engineering’s history to hold an endowed deanship. During her tenure as dean, Dr. Wei has increased extramural grants and endowment gifts, strengthened industry partnerships, and tripled corporate master’s degree programs from five to 14.”

Dr. Wei – first interviewed here on EDACafe in 2006 – has a long, distinguished career at SJSU. Her contributions to engineering education, in particular, the promotion of under-served populations who seek careers in technology, are extremely significant.

It was an honor to speak with Dean Wei this week about engineering education, innovation, and everything in between. We spoke on May 22, 2012.

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Docea: the Power and the Story

Tuesday, May 22nd, 2012

 

Docea Power, founded in 2006 in the Grenoble area of central France by brothers Ghislain and Sylvian Kaiser, now has an office headquartered in Silicon Valley. When CEO Ghislain Kaiser and I spoke by phone this morning, he talked about the company’s product offerings – in particular, those set to be showcased at DAC in San Francisco in early June.

Ghislain said, “AceThermalModeler is our new tool that is available for both architects and system designers [through which] they can create a compact thermal model for a proposed product.

“True, there are on the market today tools from Mentor [FloTHERM] and Ansys [Icepak] that do thermal analysis, but those tools need a lot of run time because they are not compact. The models they produce are accurate, but require hours and days of compute time.

“Docea’s AceThermalModeler, however, relies on fast computing – just seconds or minutes – so at the architectural and system level the design space can be explored quickly. [In fact], if we compare the models produced by our solution, we are within 5% of the models produced by Mentor or Ansys, so for a great deal of savings in time only a small amount of model accuracy is lost.

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Joe Costello: Orb, Oasys, Epicenter

Wednesday, May 16th, 2012

 

On May 1st, Joe Costello was standing in his office at Orb Networks on the 6th floor of a building in downtown Oakland. When we started our phone call, he said, “I’m looking down on Broadway and there’s a massive march out there. It’s crazy — wish I could send you the video!”

It was, of course, the May Day Occupy Oakland march, which seemed just about right for this long-planned interview.

Twenty years ago, Joe Costello was CEO at Cadence; today he’s President & CEO at Orb Networks, a company that’s “cranking away at cool stuff in the media space.” Twenty years ago, Joe Costello was the epicenter of EDA; today he’s roiling things up elsewhere in the technology ecosystem.

So first we talked about Joe’s present and future, and then we got around to EDA’s present and future and What Would Joe Do if he was back in the epicenter today.

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Eruptor: Portal of Power!

Tuesday, May 15th, 2012

 

My good friend Chas is 7 years old, and he is an expert on Skylanders. And I mean, an expert!

And because of that, I myself am now almost an expert. For instance, I know there are 9 elements: Life, Fire, Earth, Water, Tech, Magic, Air, Undead, and Legendary.

Every element has 4 Skylanders, and if you are Chas — or me — your hands-down favorite among the 32 Skylanders would be Eruptor and his magma pool. Or maybe Ignitor and his blue-flame combo. Eruptor and Ignitor, of course, are both Fire types which is why we like them so much!

Meanwhile, if you haven’t a clue what Chas and I are talking about here — or don’t know why there are 9 elements and 4 Sklyanders per element, but only 32 Skylanders in total — just ask us. Or better yet, watch the YouTube videos below and prepare to be blown away!

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DAC 2012: Thermocouple Thursday in San Francisco

Monday, May 14th, 2012

 

Why call this Thermocouple Thursday?

For two reasons. First, because the rest of the days at DAC 2012 in San Francisco got alliterated:

* Super Sunday
* Marvelous Monday
* Terrible Tuesday
* Wicked Wednesday

And second, because “a thermocouple is a device consisting of two dissimilar metals joined at two points, the potential difference between the two junctions being a measure of their difference in temperature.”*

And if that doesn’t describe Thursday, June 7th, at DAC 2012 what does?

After all, nobody really sticks around for Thursday at DAC unless a) they’re presenting on that day, b) they’ve got a client and/or student presenting on that day, or c) they’re staying through the weekend to vacation in The City.

But people not sticking around for Thursday at DAC is just wrong, because Thursday is the thermocouple day that connects the  two main parts of life in EDA.

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DAC 2012: Wicked Wednesday in San Francisco

Sunday, May 13th, 2012

 

DAC looms!

If you do nothing else on Wednesday, June 6th, at the Design Automation Conference be sure to attend the second of the two keynotes.

Intel’s Brad Heaney will be talking about “designing a 22nm Intel Architecture Multi-CPU and CPU.” It’s got well over a billion transistors and would have only been the stuff of Sci-Fi dreams a brief 15 or 20 years ago.

After that, just like on Terrible Tuesday, you’ve got a wicked wheelbarrow full of different ways you could go, starting with the User Track. The Wednesday line-up in this well-received recent addition to the DAC schedule includes:

* Packaging & Automatic P&R, with speakers from Mentor Graphics, Samsung, and Intel
* Keynoter Q&A, with the morning’s IBM & Intel speakers fielding questions from the crowd
* Practical Formal Methods, with speakers from IBM, Oski, and Intel

If your interests, however, reside with the young more than the mega-organizations in the EDA ecosystem, Wednesday is your day to visit the ACM Sigda University Booth in the Exhibition Hall, where the “new EDA tools, EDA tools applications, design projects, and instructional materials” will be your guide to the future minds of this industry.

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DAC 2012: Terrible Tuesday in San Francisco

Tuesday, May 8th, 2012

 

DAC looms!

And never more so than on Tuesday — especially this year, June 5th, when you’re going to have to make some terrible decisions about what to miss, and what not to miss.

First there’s the opening session in the morning when a boatload of awards are handed out, followed by the 2012 keynote. The Exhibition Hall won’t open until these things wrap up, so other than company meetings or company special-product announcement breakfasts, you should be able to be in the main theater at Moscone from 8:30 to 10:00 am or so.

Of course, worst case scenario: The opening session at DAC is always video-taped, so you could watch it at a later date after it’s uploaded to the DAC website but that’s hardly ideal.

This year’s main address will be delivered by ARM’s Mike Muller, “comparing the original ARM design of 1985 to those of today’s latest microprocessors … how far design has come and what EDA has contributed to enabling … systems, hardware, operating systems, and applications.” Then Muller plans to talk about 2020, how to get there, and what it will be like when we do. Conclusion? This stuff’s better heard in person than tape delayed. Go to the opening session, and plan not to regret it.

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