Archive for March, 2012
Thursday, March 29th, 2012
Here are the Top Ten reasons to be going to EDPS next week in Monterey:
10) Next week’s a lighter work week for most and the Monterey Peninsula is beautiful at any time of the year, but particularly in the spring.
9) The Electronic Design Process Symposium is in its 19th year, and everybody who’s anybody in EDA and its adjacencies has attended at one point or another.
Eight) The topics discussed at EDPS have always tracked the trajectory of the industry. In 2000, those topics included: deep sub-micron, distributed and web-based design methodologies, designer productivity, and maintaining modularity in an integrated design flow.
Here in 2012, technology evolution has driven a completely different set of topics: embedded processors, FPGAs, ESL, NUMA, EDA in the Cloud, Big Data and the Big Servers that serve them, low-power design, and 3d-ICs, among others.
7) Going to conferences is as much about conversations outside the sessions, as it is about presenting or listening within the sessions. EDPS is a boutique conference, where I promise you’ll have a chance for substantive conversations with the speakers, both inside and outside of the sessions.
Tuesday, March 27th, 2012
Design West is underway this week at the San Jose Convention Center. There are plenty of people in attendance, both in the sessions and in the Exhibit Hall, particularly at the Intel booth.
Intel’s a popular destination at the show, because they’ve got on display there a very interesting thing.
First shown at last fall’s Intel Developers Conference, it’s a musical ensemble that plays when a swarm of several thousand 1″ pellets fly up and out of various hoppers and dispensers and land on the music-making parts of the Rube-Goldberg-like contraption.
The resulting 3-minute concert is captivating from a musical point of view, and fascinating from an engineering point of view. You can see several clips of the performance below.
Saturday, March 24th, 2012
When we last left our hero – that is, Mentor’s Catapult C high-level synthesis tool – it had just been sold off to Calypto in a move that the companies said, “will create a better integrated ESL hardware realization flow.”
Now, some 7 months into the adventure, I spoke with Calypto’s recently appointed VP of Marketing Shawn McCloud at DVCon:
Shawn: Calypto specializes in the ESL hardware implementation flow. We’re accelerating design with Catapult, optimizing the design for power efficiency with PowerPro, and doing verification with SLEC, which provides equivalence checking from RTL-to-RTL, or from C-to-RTL.
Q: Who’s the competition?
Shawn: Nobody has all 3 of these products, but within high-level synthesis, it’s Forte – and yes, we are the new Mentor. For power, the competition is Apache and Atrenta, but they’re both manual solutions, while we’re automated. And, nobody has our equivalence checking capability.
Q: Your exit strategy?
Shawn: Our goal is to grow 25-to-30%, year over year, and then we will have a number of different options: acquisition, or even an IPO.
Wednesday, March 21st, 2012
Because Pallab Chattejee went to upwards of 78 technical conferences last year, he probably knows a thing or two about the status of the industry today. It also helps that he’s a long-time IC design adviser, CTO of SiliconMap, a consultancy, and is ramping up a new online publishing presence, Media & Entertainment Technologies, with long-time tech guru Tets Maniwa.
Among his many involvements, including the IEEE Nanotech Council and U.C. Berkeley’s Engineering Alumni Society, Pallab has been associated with the International Symposium on Quality Electronic Design for all of its 13 years.
He’s headed up most of the committees at one point or another, and this year is serving for a second time as General Chair, so it’s not a complete surprise that Pallab has been named an ISQED 2012 Fellow.
What is a surprise, is Pallab’s candid assessment of the messages that are often the stuff of conference keynote speeches – even those given at ISQED – particularly when those speeches are offered up by EDA vendors or foundries. (more…)
Saturday, March 17th, 2012
A lot of ink is always spilled over the EDAC CEO Forecast Panel, and this year was no different.
Ed Sperling moderated the panel and had slides to facilitate. They’re available here on the EDAC website. The full video version of the event is now available, as well.
If you would rather read about it, Mike Demler transcribed the event, Paul McClellan encapsulated the event, Richard Goering observed the event, and Steve Leibson abstracted the event.
I was also there on February 29th in Santa Clara, but rather than re-invent the wheel and provide redundant commentary, I’ve taken my notes from the evening and used them to create a Word Cloud. [see below]
If you study it carefully, you’ll see it pretty much sums up the emphasis of the panel discussion: Synopsys’ Aart de Geus, Mentor’s Wally Rhines, Cadence’s Lip-bu Tan, ARM’s Simon Segars, and Gradient’s Ed Cheng in conversation with Ed Sperling, exchanging ideas about Different Problems in EDA: Tools, Power, IP, Memory, Integration, Systems, Hardware, Software, Money and Innovation.
Now let’s look at the Word Cloud without any of the names, just the issues that swirled about in the conversation on February 29th. (more…)
Saturday, March 17th, 2012
When it comes to Westerns, nothing satisfies more than the one about long-time compadres getting together to do one last ride, one last round up, to take one last stand.
It satisfies, because it’s been years in the making and involves all aspects of the genre – long, lonely shots of distant horizons, fading references to the “exploration and settlement of previously untamed frontiers”, and a rich narrative of “rugged, self-sufficient individuals taming a savage wilderness with common sense and direct action.”
This particular type of Western also satisfies, because we know the players well – their faces, their mannerisms, how many notches they’ve got in their gun belts, and whether they normally ride alone or in a posse. (more…)
Thursday, March 15th, 2012
If you missed this week’s Blue Pearl Software workshop in Silicon Valley, you’re in luck – they’re holding it again on April 19th.
These workshops offer not only the opportunity to learn about Blue Pearl’s technologies, they’ll also let you brush up on your acronyms – FPGA, ASIC, SOC, CDC, SDC, SV, VHDL, and RTL – though not necessarily in that order.
Blue Pearl sells a suite of tools offering “comprehensive RTL analysis, clock-domain crossing [CDC] checks, and automated Synopsys Design Constraints [SDC] generation for FPGA, ASIC, and SOC designs.”
Release 6.0 was announced in February at DVCon 2012, where I spoke with Shakeel Jeeawoody, Director of Product Marketing at Blue Pearl.
Jeeawoody said, “We provide tools for linting, clock-domain crossing, and automated SDC generation – things people use to constrain their synthesis. Here in Release 6.0, a major new feature includes language coverage. (more…)
Saturday, March 10th, 2012
Even this deep into the era of IP and design reuse, it’s been my thesis that things are not quite as far along as many in the industry would like you to believe. With that attitude in hand, I spoke with three different companies in the IP space who disagree, although they admit issues still remain.
You can read my conclusions below from what they had to say, or you can read the original interviews and draw your own conclusions …
* Hal Barbour, CEO at CAST
* Warren Savage, CEO at IPextreme
* Bernd Stamme, Marketing Director at Kilopass Technology
Where things stand …
* IP is a reality: Over the last 10 years, the reluctance to buy IP has subsided, because third-party IP is better than ever, and the companies that sell it have come to see themselves principally as product companies, not services companies.
* Lots of different types of IP: Vendors are selling processor cores, standards-based busses, mixed-signal blocks, back-end design blocks, software blocks, drivers, foundation IP, etc., or any combination of the above.
* Standards and tools: Various wrapper standards and IP integration tools are easing the burden of using IP in a design.
* NIH still a reality: Concern still lingers, often without basis, that if I didn’t design it myself, I shouldn’t bank my product and my job on somebody else’s design bit.
* Risk Aversion still a reality: Buying IP is still not great for the highly risk adverse, people who need to guarantee a block is interoperable, meets required specs, and has been sufficiently deployed to work out the bugs. (more…)