Archive for 2012
Thursday, December 13th, 2012
When it comes to stimulating, it doesn’t get better than stepping out of a session at IEDM in San Francisco to take a conference call from Glasgow. On Tuesday, December 11th, I stepped out of Session 9 and a presentation on spintronics to speak with Dr. Asen Asenov about a different device technology.
Asenov is a 20-year veteran of the University of Glasgow, where he serves as James Watt Professor of Electrical Engineering and heads up the Glasgow Device Modeling Group. He is also founder of Glasgow-based Gold Standard Simulations (GSS), a company that specializes in simulating statistical variability in nano-CMOS devices.
We spoke on December 11th because GSS announced that day the results of research “comparing the differentiation between metal gate first and metal gate last FDSOI [fully-depleted silicon-on-insulation] approaches, and comparing it to equivalent bulk MOSFETs.” Based on that work, the company announced that gate-last technology “offers significant advantages” over gate-first technology for devices built on 32- or 28-nanometer FDSOI, and noted that both nodes “significantly outpace equivalent bulk MOSFETS with respect to low-power SRAM design.”
Thursday, December 6th, 2012
Shakeel Jeeawoody is VP of marketing at Blue Pearl. I enjoyed a long conversation with Shakeel at SAME Forum in France in October, and again at ARM TechCon in November. We completed the discussion by phone this week, starting with a brief profile of Blue Pearl and a discussion of FPGA versus ASIC design needs.
Per Jeeawoody, “Blue Pearl has been around since 2005, we’re located in Santa Clara, and our technology has all been developed in-house. Our underlying technology improves RTL analysis using symbolic simulation techniques and adapting them to our customers’ market requirements. We have competitors in the linting and clock-domain crossing [CDC] space, but not many that can generate SDC constraints and offer easy-to-use tools that run on Windows at an attractive price point to support FPGA designers.
“More FPGA designers today struggle with IP integration in their projects in the same way ASIC designers have in the past; if they don’t do the right level of analysis, there are reliability problems in the field. With that in mind, we focus on addressing emerging and major FPGA design issues – one we call Grey Cell Methodology, and we offer mode-based analysis to address issues associated with longest path analysis.
Thursday, November 29th, 2012
You’ve got a little over a week to clear your calendar to attend two very important conferences spanning the week of December 10th to the 14th. IEDM is happening in San Francisco from December 10th to 12th, and the 3-D Architectures for Semiconductor Integration and Packaging Conference is happening in Redwood City from December 12th to 14th.
These are two well-attended and carefully constructed conferences which many people attend to learn about the latest in device engineering and 3D-IC architectures, both key to the future of the semiconductor industry.
Clearly, December is a busy month. If you’re in Sales, you may be trying to maximize your numbers for the quarter, and the year, over the remaining weeks of 2012. If you’re in R&D, you may be trying to utilize budget dollars that come with ‘use it or lose it’ strings attached. If you’re in Field Support, your customers are stressed, short on time, and need your attention sooner, not later, so they can wrap up their projects before their holiday leave begins. And if you’re that customer, the Designer trying to meet a development schedule, you are really strapped for time.
Thursday, November 22nd, 2012
If you are looking for an opportunity to express your satisfaction with a colleague’s contributions to the world you work in, two outstanding chances currently present themselves. But take care: The deadlines for submitting your nominations quickly approach.
First, Accellera Systems Initiative [a.k.a. Accellera] has set January 18th as the deadline for submitting nominations for its 2013 Technical Excellence Award. Per the organization: “The Award recognizes outstanding contributions in the creation of EDA and IP standards [which are then contributed to the IEEE Standards Association] by a member of an Accellera technical committee.
“Any individual who is a member of an Accellera technical committee is eligible to receive the award, which will be presented at Accellera Systems Initiative Day during DVCon 2013 next February in San Jose. Candidates may be nominated by the industry at large and are endorsed by Accellera committee members. To nominate an individual, visit Accellera.org.”
If you want to do something really dramatic, however, the EDA Consortium is currently accepting nominations for its annual EDAC/CEDA-sponsored Phil Kaufman Award, which these organizations frequently refer to as the Noble Prize of EDA.
Wednesday, November 14th, 2012
It’s a bit early for New Year’s Resolutions, but Real Intent has gotten a jump on the popular annual ritual. As of today, the company is declaring “a bold new look for its corporate logo and Web-site, and a new location for its headquarters.”
The press release reiterates Real Intent’s offerings – Ascent, Ascent Lint, Ascent Implied Intent Verification, Ascent X-Verification System, Meridian, Meridian CDC, and Meridian Constraints – and says, “with the capabilities [of these products] in mind, Real Intent re-imagined its logo to mimic the real intent of these software offerings. The familiar white and blue logo now is recast with striking simplicity.
“The new ‘look’ graphically parallels the simplicity and speed with which SoC designers can use Real Intent’s technology. The transformation mirrors Real Intent’s evolutionary change from an EDA formal verification company to a best-in-class verification solution company. Real Intent has also transformed its Web-site with a dramatic, clean new look and simple navigation that parallels the simplicity and ease of use of its solutions.”
Now, you may say that all of this is being done just to catch the eye of a jaded public, but consider how hard change really is.
Monday, November 12th, 2012
If you’re an IP developer, or somebody who develops SoCs where blocks of IP land, Synopsys is announcing a product today that will be of interest: the HAPS-70 Series. It’s a prototyping system with a distinguished provenance that runs your ASIC-targeted design on FPGAs for validation prior to tape-out.
HAPS-70 started its journey to your work place way back in 1987 when Sweden-based HARDI Electronics was founded. The folks at HARDI developed the original HAPS prototyping system, which became part of Synplicity’s arsenal in 2007 when HARDI was acquired by SYNP, and the product was relaunched as HAPS-54.
Gary Meyers was President and CEO of Synplicity at the time, and was quoted: “This is a major strategic move for Synplicity. We will be able to immediately leverage our existing ASIC verification products (Certify, Synplify Premier, Identify, and Identify Pro) by selling them together with the HARDI ASIC prototyping boards.”
Thursday, November 8th, 2012
It might be the impression of late that all EDA-startup roads lead to Synopsys, but that would be incorrect. Small, privately-held companies continue to make their way in the industry, independent and productive.
Ausdia, based in Silicon Valley, has been underway since 2006 developing tools for timing constraint verification and management. Today the company announced a new board member, Sanjay Lall. Per the press release, Lall has 20+ years of experience in the EDA and semiconductors, “an expert in operations, marketing, fund raising and sales.”
He is also Chairman and Managing Partner at Cronox Group, on the Board of Advisors at Verdigirs Technologies, and a Director at Mobi-holdings. Previously, Lall was VP of Sales at Extreme DA, and “influential in the company’s acquisition by Synopsys in 2011.”
All EDA-startup roads may not lead to Synopsys, but not surprisingly the CVs of most seasoned EDA veterans do lead to Synopsys, and/or to Cadence and/or Mentor Graphics.
Thursday, November 1st, 2012
The leadership of ProPlus Design Solutions has a long history in EDA, although the company itself is a newly launched startup. Ten years ago, the majority of the leadership were involved in Celestry Design Technologies, Inc., while 5 years ago all of today’s ProPlus executive team were at Cadence. Today the company, based in Silicon Valley, is building on those many years of experience to make inroads in the demanding market for design-for-yield tools.
In late September, ProPlus released its newest product offering, NanoYield for yield prediction and design optimization. When I spoke with Dr. Zhihong Liu, Executive Chairman of the company, he touched on the history of ProPlus and explained the intent of NanoYield.
Per Liu, “ProPlus has foundation technology in modeling that goes back to Celestry, a company acquired by Cadence in 2003. When the team bought the technology out of Cadence, they founded ProPlus and [worked to create] a unique DFY solution, design for yield.
“Before I joined ProPlus two years ago, they were developing lines of technologies for both high-performance parallel modeling and circuit simulation/analysis with true SPICE accuracy. Now we have put everything together to provide an integrated solution for designing better circuits in shorter time, including modeling, simulation and multivariate statistical analysis. No one else in the industry is addressing all three of these together.
“One technology that was originally licensed from IBM is a multivariate High-Sigma solution. We put that together with our own industry-validated solution, and now provide the only integrated solution in the industry, NanoYield.”
Wednesday, October 31st, 2012
Today is Halloween on both the East Coast and the West Coast of the United States. Millions of children on both ends of the country will be arriving at school in full costume regalia, prepared for parties, parades, and cheerful pandemonium. There is a major difference, however, between the events that will be unfolding in two specific locations on these two coasts.
In the San Francisco Bay Area on the West Coast, hundreds of thousands of children will be going to school in costume, while some hundreds amongs those thousands will be playing hookey, with their parents’ permissions, in order to stand on Market Street in The City and be part of the spectacle and ticker-tape parade celebrating the World Series winning San Francisco Giants.
In the New York/New Jersey metropolitan area on the East Coast and beyond, however, millions of people will spend this same day not celebrating at all. Instead they will be enduring another day without power or heat, only venturing out for food as needed from darkened shops, while having to slog through mud, sand, and the shattered remnants of their communities to do so.
Thursday, October 25th, 2012
Montreal is not a place that normally comes to mind when you think of EDA. Space Codesign Systems, however, is on a fast track to change that in a classically Canadian way – calm, cool, and collected.
When I spoke with General Manager Dr. Gary Dare on a beautiful afternoon in Southern France at SAME Forum in early October, he explained how the company started in Canada, and the road map they have set out for themselves: “We’re an EDA company, an EDA startup, and we are definitely based in Montreal. If you doubt that EDA has a place in Canada, we will soon convince you otherwise.
“Space Codesign comes from the acronym, SystemC Partition of ACE, which was the 2004 research project at the Ecole Polytechnique [University of Montreal] that our technology is based on. In 2008, Professor Guy Bois and various graduate students associated with the project decided to do a spin-out, and in 2010 Space Codesign Systems went into operation.”
He laughed and added, “Our company has nothing to do with space, however. But it has everything to do with hardware/software co-design – doing it simultaneously, rather than the usual way of ESL hardware design followed by software design. The audience we are targeting is the systems architects who are looking at the algorithmic level and need a route to design exploration and implementation. Our tools give them that route.