EDA Weekly Review November 29th, 2012

Angisys: Efficient Design Verification
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December 10th to 14th: IEDM & 3-D Architectures
November 29, 2012  by Peggy Aycinena

 

You’ve got a little over a week to clear your calendar to attend two very important conferences spanning the week of December 10th to the 14th. IEDM is happening in San Francisco from December 10th to 12th, and the 3-D Architectures for Semiconductor Integration and Packaging Conference is happening in Redwood City from December 12th to 14th.

These are two well-attended and carefully constructed conferences which many people attend to learn about the latest in device engineering and 3D-IC architectures, both key to the future of the semiconductor industry.

Clearly, December is a busy month. If you’re in Sales, you may be trying to maximize your numbers for the quarter, and the year, over the remaining weeks of 2012. If you’re in R&D, you may be trying to utilize budget dollars that come with ‘use it or lose it’ strings attached. If you’re in Field Support, your customers are stressed, short on time, and need your attention sooner, not later, so they can wrap up their projects before their holiday leave begins. And if you’re that customer, the Designer trying to meet a development schedule, you are really strapped for time.

Bake sale: CEVA’s unsolicited offer to buy MIPS
November 29, 2012  by Peggy Aycinena

 

In a move to catch up with industry coverage of CEVA’s unsolicited offer to buy MIPS Technologies, I turned to Yahoo Financials to find out what was going on. What I quickly discovered in looking at Yahoo was that the CEVA/MIPS story has gotten ugly.

I’m among many who have been interested in MIPS over the years for several reasons: a) MIPS used to be on the EDAC Board of Directors in the person of then-MIPS President & CEO John Bourgoin, and b) MIPS was founded by Stanford President John Hennessy.

Now, however, per the Press Release posted on November 28th: “Levi & Korsinsky is investigating the Board of Directors of MIPS Technologies, Inc. for possible breaches of fiduciary duty and other violations of state law in connection with the sale of the Company to Imagination Technologies Group PLC and the sale of the Company’s patents to Allied Security Trust (“AST”).

The “Macro Cycle” at The End of 2012
November 29, 2012  by Charlie Cheng

The Semiconductor business cycle was somewhat predictable in the good old days with the next node capacity expansion plan and PC upgrade cycle dominating the discussion on the size and timing of the cycle.  The 1990s ushered in the correlation of the semiconductor growth with the global economic cycle, and the business has not been the same ever since.  It’s much more dependent on the health of global economy, and more dependent on human factors difficult to predict.

At the beginning of 2012, there were two macro factors that could have affected the semiconductor business: the EU “grand compromise”, and the Pacific Rim elections.  The fear of an exit of either Greece (or Germany) causing a run in credit never did come to fruition, instead a compromise was patched together to allow EU to last another year or two without addressing its long term structural issues.  Likewise, the fear of incoming governments with unyielding political ideologies creating a Pacific Rim showdown also seem unlikely now, with Taiwan, China, US, and soon Korean elections all resulting in “more-of-the-same” government.  The global GDP maybe heading towards a 4 percent growth (instead of 5 percent), but the slight slowdown isn’t due to some abrupt changes in politics, but rather the rapid maturation of developing countries. Thus, 2012 will soon end pretty much how it was predicted, with little government-caused disaster (but not much help, either).  Apple continues to set the pace for the market on innovation, and Samsung-Google driving the volume growth in smart mobile platform.  The concentration of platform has caused the winners to take more, and losers to lose all.

Khan Academy- I’m a Fan!
November 29, 2012  by Sherry Hess

A few months ago, I heard a news program on NPR about the Khan Academy and how it was started accidentally by Mr. Khan to help his niece with her math homework. Since he lived far away from her, he captured his helpful hints via YouTube and shared via the Internet. One thing led to another and now Khan has found himself the creator of something big.

Since that NPR special, I’ve had a few chances to visit the website. There are over 3,200 videos on a wealth of subjects. I found myself touring around and clicking on things like art history, science, economics, history and even SAT prep, and getting progressively more excited by the proposition that this is a tipping point to excite kids to continue to be curious about math and science as they get older.

The Khan Academy concept reminded me of Professor Fornetti’s ExploreRF YouTube Channel, which offers training courses and webinars in RF and microwave related subjects, and of course AWR’s own AWR.TV portal. Our numerous video tutorials and vignettes are meant to accomplish the same for RF/Microwave education as Khan is for mathematics.  Both aim to excite current and future users to learn more about the wealth of capabilities in AWR’s software as well as the fundamental mathematic theories it solves.

AWR continues to be committed to helping university students learn more about RF/microwave design. To that end, we recently ran a contest to see if our strategies of supporting university engineering courses, awarding free software to engineering graduates, and sponsoring the IMS and EuMW Student Design Contests were having a positive impact. We were excited to find many success stories, two of which we have recently published. One design student at Istanbul University of Technology (read the story here>>) actually taught himself how to use Microwave Office through our documentation, extensive library of examples, and, most importantly, our AWR.TV videos. His journey resulted in a low noise amplifier design that won the Turkey Graduation Design Competition and was a finalist at the IMS Student Design Competition. Another student from Vienna University of Technology (read the story here>>) was able to design an X-band transmission analyzer from end to end thanks to several master’s degree courses that offered the use of Microwave Office, as well as attentive technical support. His design won the IMS Student Design Competition. Details on both of these stories can be found in the success stories included in this newsletter.

Stale IP – another view
November 26, 2012  by Ed Lee

In my last blog, Harrison Beasley shared his views on stale IP.  This week we hear from Manoj Bhatnagar, Senior Director, Field Delivery and Support at Atrenta.

Liz:  Manoj, what is stale IP?

Manoj:  An IP may become stale because either its specifications have changed (e.g., USB 1.0 vs. 2.0 vs. 3.0) or there is a better implementation available (e.g., a graphics core is now running at 800Mhz instead of 500Mhz). Typically, people will use the latest version, and the older versions are no longer used.  So the stale IPs in this case will die a natural death. What is more challenging, however, is a specific IP developed for a specific project and, over time, no other project used it.  So the IP becomes stale. Most of my answers will apply to this type of stale IP.

Liz:  What’s so bad about it?

Manoj:  The main issue with a stale IP is the fact that nobody really knows the details about it. If I were to use that IP, I would be putting my design at risk because I am now adding some logic to my design for which I don’t have all the information and can’t find anyone who can provide that information either.

Liz:  How do we prevent it from being stale? 

Manoj:  One of the key things that can be done to prevent IP from going stale is to document the IP. I don’t know how many people still remember the TTL datasheets but when you looked at the datasheet, you got complete visibility into what that component did. The same concept can be applied to present day IPs, where you document various characteristics of the IP. For a hard IP, this may be the timing characteristics, physical profile, etc. while for a soft IP this may be timing constraints, clock domain information, testability profile and power profile.

DVCON 2013


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