EDACafe Weekly Review May 28th, 2015

The last two weeks before the Design Automation Conference in San Francisco are a busy time.  For us marketeers, it has been called “our Superbowl.”  We want to get the word out that we have something new and important to show visitors to at our exhibit booth.  But there is more going on which I will mention after I talk about our booth activities.

Real Intent is number two on the GarySmithEDA What to See @ DAC list.   I know why we are number two on the list.  But I don’t want to give the secret away. If you know the reason, then please let everyone know in the comments section at the end of the blog.

Here are the quick titles for our technical presentation in our demo suites.

  • Ascent Lint with 3rd Generation iDebug Platform and DO-254
  • Meridian CDC for RTL with New 3rd Generation iDebug Platform
  • Ascent XV with Advanced Gate-level Pessimism Analysis
  • Accelerate Your RTL Sign-off
  • Hierarchical CDC Analysis and Reporting for Giga-gate Designs
  • Next-Generation Meridian Constraints for SDC
  • Autoformal RTL Verification
  • FPGA Sign-off and Verification

Click on this appointment sign-up link to arrange a meeting with us.

Memorial Day has come and gone, which means two things: summer is here and DAC is officially upon us. In just over a week the doors will open at Moscone Center with a blockbuster designer keynote: Brian Otis, director of Google’s smart contact lens project. Brian, the first Googler to ever take DAC’s main stage, is just one reason to consider registering for the designer and IP tracks if you haven’t already. Others include access to great lineup of marketing-free, engineer-to-engineer sessions, daily networking receptions (yes, you grown-up undergrads, there will be lots of free food and drink), the rest of the keynotes (did you know DAC is also welcoming a MacArthur genius this year?) and of course the exhibit floor. Not bad for just $95.

Portable Stimulus Layer 3: Test Randomization
May 28, 2015  by Tom Anderson, VP of Marketing

Over the lifetime of this blog, we’ve covered a lot of diverse topics regarding Breker’s products and technology, trends in SoC verification, and the EDA industry in general. For the last month, we’ve offered our longest series of posts ever on a single topic: portable stimulus. There’s a very good reason for this: Accellera’s Portable Stimulus Working Group (PSWG) is making good progress on defining a standard in this area. As one of the group’s leaders, Breker has been leveraging our many years of experience in SoC verification to develop the best possible industry solution. We’ve been using The Breker Trekker blog to share our thoughts and to encourage your feedback.

We begin the fifth, and perhaps most important, post in our series by reminding you that we split portable stimulus into three layers: defining the tests using abstract primitive operations, scheduling the tests across multiple threads and multiple processors, and randomizing the control flow to verify the full range of realistic use-case scenarios. We have shown over the last two posts that both the first and second layers can be defined easily by a simple application programming interface (API) providing access to a base-class library. This library includes the basic building blocks needed for a directed or automated test as well as scheduling control for processors, threads, and resources. It is natural to wonder whether the randomization layer can be handled in a similar way.

Emulation Takes Center Stage
May 27, 2015  by Lauro Rizzatti

Emulation is enjoying its moment in the spotlight and none too soon. Design complexity of all types has conspired to make chip verification an arduous task. These days, the fabric of system-on-chip (SoC) designs includes several processing cores, large sets of specialized IP, a plethora of peripherals and complex memories, routinely pushing the design size into the hundreds of million gates. Embedded software now exceeds the complexity of the hardware.

Consider that for each hardware designer there are at least five software developers. No surprise that chip verification and validation has become an overriding concern for all project teams, particularly when hardware and software integration is concerned. Here is where the rubber meets the road, and where the verification challenges reach their peak.

Design rules built on quicksand?
May 27, 2015  by Ed Lee

 

Sage CEO Coby Zelnik recently talked with us about how design rules need a formal methodology to account for all the permutations of each rule for today’s and the next generation’s chip designs.

What I found alarming was that he noted how design rules are being built today.   An engineer writes the rule based on…well, based on…um…gut feel?    The point is that the design rule creation process currently has no specification to govern the creation of the design rule.

Tortuga Logic: Expect the Unexpected
May 26, 2015  by Peggy Aycinena

 

If you’re a Spanish speaker, the first image that comes to mind when someone says tortuga is a slow-moving animal in a shell. Alternatively, if you’re a kid at heart and love pirates, the first image that comes to mind when someone says Tortuga is Johnny Depp sashaying around the Caribbean channeling Keith Richards.

If you work in EDA and/or use EDA tools, however, now a new image should come to mind when someone says tortuga: The image of a secure, buttoned-down design that’s impervious to harm, malicious intent, or even too much eye-liner (for the Depp/Richards fans out there).

Because a new company has just come up over the horizon: Tortuga Logic.

Built on IP developed by like-minded thinkers at U.C. San Diego and Santa Barbara, Tortuga hopes to change the way the world deals with security issues — which, by the way, is an even bigger problem today than it was back when Captain Jack Sparrow was wreaking havoc on the Spanish Main.

Some innovations give such an exponential productivity shift that they are often only appreciated when viewed with the perspective of history. Isambard Kingdom Brunel built the first train line from London to Bristol and cut down the travel times from days to hours. In doing so he actually moved time itself; at the time Bristol was 30 minutes behind London. Clocks in the 19th century were based off sunrise and sunset in each location as it was never necessary to be so precise when travel between two places meant a much longer journey. However the real benefit he provided was literally giving time to people, by shortening the travel time it enabled people to dedicate time to solving other problems. The spread of train tracks across the UK and the rest of the world enabled the rapid development of the Industrial Revolution that provided the foundation for the modern world. There is a fantastic documentary on Isambard Brunel on YouTube for those who wish to find out more.

 

Clifton suspension bridge

The Clifton suspension bridge in Bristol. A revolutionary construct in 1864 that dramatically cut travel times between London and Bristol

Innovation: Thy name is eSilicon
May 25, 2015  by Peggy Aycinena

 

While news last week out of eSilicon proved again the company’s ability to innovate and build on emerging technologies, a phone call with company VP Mike Gianfagna also proved something: Mike continues to be one of the ablest spokesmen in the industry. Very helpful, because the news is not simple.

On May 19th, the company announced STAR platform, the Self-service, Transparent, Accurate, Real-time platform. Per the press release, “STAR supports eSilicon’s existing IP browsing, instant quoting, and work-in-process tracking capabilities, along with a new chip optimization offering that leverages design virtualization technology. The platform also delivers an enhanced user interface with simplified account setup and access.”

Oh yeah, and the company also announced they’ve unified and re-branded their tools:

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