February 28th, 2013
I don’t know about you, but I thought DVCon 2013 in San Jose this week was super. There was a lot of energy, I never heard anybody say the tools are broken (something industry pundits have been droning on about for years), attendance at the conference set a new record, both verification and design guys seemed to indicate that verification is still important enough to remain discrete from design, and SystemVerilog is fulfilling its promise.
The following list of 15 sound bites is not a complete representation of all that was said or debated at DVCon. Nonetheless, it’s an interesting list and reflects some of the information and opinions showcased during the week.
We just finished a BUSY week of activity at the Design and Verification Conference. The exhibits were open for 3 hours on Tues. and Wed. in the late afternoon. The floor was buzzing when the technical program was done for the day and the beverage bar helped to fuel everyone’s spirits. I think floor traffic may have been lighter than earlier years, but the floor layout was definitely more conducive for people to move around.
Vaishnav Gorur, Sr. Field Applications Engineer, at the Real Intent DVCon 2013 booth
Real Intent sponsored a panel, “Where Does Design End and Verification Begin?”, which had over 140 attendees listen to experts from ARM, Mentor Graphics, Intel, GarySmithEDA, and Real Intent. The discussion was lively and the moderator, Brian Hunter from Cavium, threw at least one gibe. I knew it was a very good panel when attendees were echoing the discussion at another panel later that day. I had my video camera recording the back-and-forth and will be posting clips from the panel in the weeks ahead on this blog.
If you’re free on the evening of Thursday, March 14th, you should plan on attending EDAC’s annual CEO Forecast Panel. It promises to be full of executive content, albeit perhaps a bit light on forecast content, but oh well. That’s the nature of life in the Publicly Traded Fast Lane these days.
Along with the CEOs of Mentor Graphics, Cadence, Synopsys, and Nimbic, the president of ARM will also be on stage, Simon Segars. Segars is no stranger to public speaking. You can hear his recent ARM TechCon 2012 keynote here. But it’s not what Segars will say on stage at the DoubleTree Hotel in San Jose on March 14th that matters. It’s his body language, and you’ll only be able to read that if you’re in the room.
Sometimes magic happens at panel discussions at technical conferences, and that was the case mid-day on Wednesday at DVCon in San Jose this week, where the conversation was lively, entertaining and informative on the pedestrian, albeit foundational, topic of “Best Practices in Verification Planning.”
Ironically, the hour-long conversation did not appear to be planned at all, but to be organic and spontaneous. The Cadence-sponsored lunch and panel discussion, moderated by Cadence’s John Brennan, included Verilab’s Jason Sprott, Cadence’s Mike Stellfox, ParadigmWorks’ Ambar Sarkar, Maxim’s Neyaz Khan, Oski Technology’s Vigyan Singhal, and Xilinx’ Meirav Nitzan. The panelists began with an overview of their experiences.
WOW, the top 1% of viewed profiles on LINKEDIN…actually my profile Mark Gilbert, but they are one and the same…see the award below (though would have preferred something in GOLD)…I am indeed quite excited, imagine anyone in EDA hitting that, let alone this little ol (not old) recruiter.
Last column I wrote about interviewing ideas for Sales folks…this time I am writing specifically to you technical engineering types hoping to help you avoid the simplest of interviewing calamities. It is absolutely amazing how many candidates, regardless of experience and accomplishment, make the most basic mistakes that cost them a second interview. So read this and take it to the bank…my advice will make a huge difference in your probability of having a successful interview.
At this week’s DVCon 2013 conference, the IEEE Standards Association (IEEE-SA) and Accellera Systems Initiative (Accellera) have jointly announced the public availability of the IEEE 1800 SystemVerilog Language Reference Manual at no charge through the IEEE Get Program.
As I posted a few weeks ago, the 1800-2012 is not a major revision of the standard, but does contain a few enhancements that will be of interest to design and verification engineers alike. However, providing the standard as freely available download is major news.
Even though the relative cost of the LRM was minor compared to the cost of most projects utilizing the standard, there seemed to be a barrier in most engineer’s minds in justifying the expense. So most just continued to use the last freely available SystemVerilog 3.1a LRM, which was 9 years old and very obsolete for such a rapidly changing technology.
So you thought our blog last week was our last prediction? Just kidding.
We actually have one more prophesy……from Michel Courtoy, esteemed EDA executive, entrepreneur and angel investor.
“As a member of the EDA community, when I look at 2013, I see a key dynamic in our customer base: chip = SoC. Across the board now, designs are created by combining multiple IPs from different sources that include embedded processors, multiple interfaces and memories. This is true across the spectrum from simple microcontrollers, to multi-function chips for consumer devices, all the way to the most complex multi-core microprocessors. Hence technologies that accelerate the design and verification of SoCs will thrive while technologies targeting the IP-level will find a saturated market.
Internal to the EDA market, we have been bombarded with messages of gloom triggered by the consolidation that has eliminated most ‘mid-size’ EDA suppliers, leaving mainly the ‘Big 3 and the 100 dwarfs’. Well, this might be the opportunity that the start-ups need: where will the Big 3 fill their shopping cart now when looking for new technologies? To stay competitive, the Big 3 have to go back to acquiring start-ups and find a way to monetize new technologies in their sales channel. This will reinvigorate the ecosystem for EDA start-ups and lead to more innovation.
Today I would like to share some basic things on ‘final’block in System Verilog. This is a newly added feature in System Verilog over Verilog. Final block is good for summery information. You can have summery information printed in log file at the end of simulation.
Final block executes at the end of the simulations without delays. ‘final’ block is like an initial block in SV only difference is that it occurs at the end of the simulations. Final block does not allow delays and time consuming or blocking activities and because of this reason it typically used in display statistical information on simulation result. Final block executes in zero time. Considering this nature of execution it is similar to ‘function’.Function also executes in zero time and does not allow timing related or blocking type of activities.
The X-band frequency range has been designated for critical military and public safety applications such as satellite communications, radar, terrestrial communications and networking, and space communications. It is important to ensure that these signals deliver quality, reliable, and secure communications. This application note describes the design and realization of a complex X-band transmission analyzer for use in real-time material testing.
The purpose of this analyzer is to gather complex-valued X-band transmission coefficients at high update rates of greater than 100,000 measurements per second. This note describes how manufacturing costs were minimized by integrating the many RF components in the device onto a single printed circuit board (PCB), how coupling issues between the RX and TX paths caused by the requirement for high dynamic range were addressed, and how EM simulator based tuning was used for the numerous distributed elements on the board to ensure optimal performance.
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