May 24th, 2012
John Cooley just published the first group of “edgy” questions submitted for his troublemaker panel at DAC. I must say the questions are almost all relevant, but very few will be answered. All the questions related to lawsuits, all the questions related to market share, all the questions related to top users of a specific product, all questions related to possible acquisitions, and all questions that ask why executives of a particular company are apparently stupid will of course not be answered. So, the collection of questions is a very well thought out vehicle to let users and competitors blow out steam, but certainly not to shed light on the industry. This will be another “EDAC CEO Panel” style event. It may make for good entertainment, John is always entertaining, but will yield very little knowledge.
At the center of the technical universe sits Silicon Valley. At the center of Silicon Valley sits the City of San Jose. At the center of the city sits San Jose State University, and at the center of the university sits the Charles W. Davidson College of Engineering.
Currently, SJSU offers 12 undergraduate majors in engineering, 11 graduate majors, and a host of different inter-disciplinary programs at all levels. It’s a dynamic College of Engineering and a powerful magnet for study in Northern California.
Dr. Belle Wei (M.S.E. Harvard, Ph.D. U.C. Berkeley) has been Dean of the College of Engineering since 2002, and is now serving a second 6-year term. On Monday, June 4th, at the Design Automation Conference in San Francisco, Dean Wei will receive the 2012 Marie R. Pistilli Achievement Award.
Per the press announcement of her Marie R. Pistilli award: “Dr. Wei is the first person in the College of Engineering’s history to hold an endowed deanship. During her tenure as dean, Dr. Wei has increased extramural grants and endowment gifts, strengthened industry partnerships, and tripled corporate master’s degree programs from five to 14.”
Dr. Wei – first interviewed here on EDACafe in 2006 – has a long, distinguished career at SJSU. Her contributions to engineering education, in particular, the promotion of under-served populations who seek careers in technology, are extremely significant.
It was an honor to speak with Dean Wei this week about engineering education, innovation, and everything in between. We spoke on May 22, 2012.
The DAC frenzy has begun. We at Jasper are excited to be going to DAC and showing the industry the latest in our leading Jasper formal technology.
We recently introduced our JasperGold Apps that help customers achieve substantial productivity gains in design and verification through individual Apps within a shared interactive environment that fit into existing verification flows. The JasperGold Apps helps solve engineers’ toughest problems, addressing an array of design and verification functionality issues throughout the flow, such as:
- End-to-end property verification,
- Unexpected X detection and debugging,
- Chip-level connectivity,
- Automated assertion generation,
- Identification of coverage holes,
- Design trade-off analysis,
- Absence of deadlock,
- Cache coherency,
- And many more.
You can see the JasperGold Apps in action in our booth.
Docea: the Power and the Story
May 22, 2012 by Peggy Aycinena
Docea Power, founded in 2006 in the Grenoble area of central France by brothers Ghislain and Sylvian Kaiser, now has an office headquartered in Silicon Valley. When CEO Ghislain Kaiser and I spoke by phone this morning, he talked about the company’s product offerings – in particular, those set to be showcased at DAC in San Francisco in early June.
Ghislain said, “AceThermalModeler is our new tool that is available for both architects and system designers [through which] they can create a compact thermal model for a proposed product.
“True, there are on the market today tools from Mentor [FloTHERM] and Ansys [Icepak] that do thermal analysis, but those tools need a lot of run time because they are not compact. The models they produce are accurate, but require hours and days of compute time.
“Docea’s AceThermalModeler, however, relies on fast computing – just seconds or minutes – so at the architectural and system level the design space can be explored quickly. [In fact], if we compare the models produced by our solution, we are within 5% of the models produced by Mentor or Ansys, so for a great deal of savings in time only a small amount of model accuracy is lost.
Article source: Cortus
Cortus extends its family of 32 bit modern RISC microcontroller IP cores with the energy efficient APS3R. The APS3R is aimed at low power embedded applications such as wireless sensor networks, touchscreen controllers, smart cards and systems using energy harvesting.
Cortus, a technology leader in ultra low power, silicon efficient 32-bit processor IP, announces the release of the latest member of their processor family: the energy efficient APS3R. The APS3R builds on experience with the earlier APS3 core but delivers improved computational performance. For more demanding embedded applications a dual core configuration is possible.
APS3R Dual Core
The Cortus APS3R is a 32-bit processor designed specifically for low power embedded systems featuring a 32-bit modern RISC architecture with sixteen 32-bit registers and a 5-7 stage pipeline. It is the second member of the Cortus microcontroller IP core family to be released in 2012 complementing the single precision floating point FPS6 core.
You are registered as: [_EMAIL_].
CafeNews is a service for EDA professionals. EDACafe.com respects your online time and Internet privacy. Edit or Change my newsletter's profile details. Unsubscribe me from this newsletter.
Copyright © 2017, Internet Business Systems, Inc. — 25 North 14th Steet, Suite 710 San Jose, CA 95112 — +1 (408) 882-6554 — All rights reserved.