March 22nd, 2012
IBM has a long history of innovation in the field on electronic design automation (EDA), beginning in the 1950’s when IBM started mass-producing computers. Engineers saw the need to control and streamline production and began using early computers such as the IBM 704 to document designs and to check the correctness of the Boolean equations specifying the behavior. In the decades that followed, IBM continued facing new challenges and solving them with pioneering inventions including circuit simulation, static timing analysis, Boolean comparison, cycle simulation, hardware acceleration, logic and physical synthesis, large scale physical design, layout checking and automated testing in manufacturing.
This video, Inside IBM EDA: 50 Years of Innovation, describes some of the innovations developed at IBM through a series of interviews with a few of the original pioneers. A small team of volunteers from IBM’s EDA community created this video for an internal workshop. They are now making it available for a larger audience.
3D in Monterey
March 22, 2012 by Ed Lee
EDPS is coming up again! It’ll be held April 5-6, 2012 at the Monterey Beach Hotel in Monterey California.
This year, the 3D topic will be the focus of day two.
First and foremost, Riko Radojcic, director of engineering at Qualcomm, will be talking about the 3D IC roadmap as the keynote speaker on day two. (see his views on 3D standards: http://www10.edacafe.com/blogs/ed-lee/2011/04/11/riko-radojcic-on-3d-standards/
Following the 1-hour keynote will be four 1/2 hour talks on various specific 3D-related topics:
* Stephen Pateras of Mentor on BIST for 3D ICs
* Arif Rahman of Altera on FPGA design challenges, presumably 3D ones
* Marc Greenberg of Cadence on the wide-IO standard for putting memory stacks on processors
* Sandeep Goel of TSMC and Bassilios Petrakis of Cadence on an end-to-end test flow for 3D IC stacks
Then there’s a lunch panel on 3D, moderated by Steve Leibson of Cadence, with these panelists addressing: The short-, medium and long-term path to the 3D Ecosystem.
* Herb Reiter
* Samta Bansal of Cadence
* Dusan Petranovic of Mentor
* Deepak Sekar of Monolithic 3D
* Steve Smith of Synopsys
* Phil Marcoux of PPM Associates
Herb is arguably the primary 3D observer and advocate on what technologies have to be in place to handle the upcoming 3D challenge that’s starting to hit designers now.
John Swan is the General Chair of EDPS 2012. Herb Reiter is the Session Chair for the keynote, four shorter presentations and the panel discussion during “3D Day”, Friday, April 6.
Very worthwhile to attend if you can get the time off.
Because Pallab Chattejee went to upwards of 78 technical conferences last year, he probably knows a thing or two about the status of the industry today. It also helps that he’s a long-time IC design adviser, CTO of SiliconMap, a consultancy, and is ramping up a new online publishing presence, Media & Entertainment Technologies, with long-time tech guru Tets Maniwa.
Among his many involvements, including the IEEE Nanotech Council and U.C. Berkeley’s Engineering Alumni Society, Pallab has been associated with the International Symposium on Quality Electronic Design for all of its 13 years.
He’s headed up most of the committees at one point or another, and this year is serving for a second time as General Chair, so it’s not a complete surprise that Pallab has been named an ISQED 2012 Fellow.
What is a surprise, is Pallab’s candid assessment of the messages that are often the stuff of conference keynote speeches – even those given at ISQED – particularly when those speeches are offered up by EDA vendors or foundries.
The Common Platform Technology Forum 2012 took place at the convention center in Santa Clara, CA on March 14th. The Common Platform is an alliance of Samsung, IBM and GLOBALFOUNDRIES to deliver foundry services using the same silicon platform. I had the pleasure of listening to the Keynote addresses in the morning and visit the Partner Pavilion in the afternoon to see all the ecosystem partners for the Common Platform. Since it was “PI day” (3/14), we enjoyed pie-on-a-stick at break time between program events. You can see what that looks like in the photo gallery below.
Follow the links to listen to each of the Keynotes:
Dr. Gary Patton, Vice President of Semiconductor Research and & Development Center, IBM spoke on “Is Scaling Over? or Is there a Future in Silicon and Beyond?”
Subramani Kengeri, Head of Advanced Technology Architecture, Office of the CTO, GLOBALFOUNDRIES spoke on “Winning Together – Driving Innovation through Strategic Collaboration”
Dr. Jong Shik Yoon, Senior Vice President of Semiconductor R&D, Samsung spoke on “3D Device Technologies – Opportunities and Challenges”
Simon Segars, Executive Vice President and General Manager, Physical IP Division, ARM spoke on “Collaborative Scaling to 14nm and Beyond”
This video presentation covers the integration of AWR’s Visual System Simulator with National Instrument’s Labview and is presented by Gent Paparisto.
Gent Paparisto, Ph.D., is a Senior Systems Engineer at AWR. He received his Ph.D. in electrical engineering from the University of Southern California (USC) and has extensive experience in research, design, development, and implementation of communication systems and algorithms for wireless, satellite, and wireline applications. He has lead and participated in the design and implementation of several products for cellular and wireless systems. Dr. Paparisto has authored a number of publications in international journals and conferences, served on the technical program committees of various IEEE conferences and contributed to the 3GPP GERAN standardization group.
A lot of ink is always spilled over the EDAC CEO Forecast Panel, and this year was no different.
Ed Sperling moderated the panel and had slides to facilitate. They’re available here on the EDAC website. The full video version of the event is now available, as well.
If you would rather read about it, Mike Demler transcribed the event, Paul McClellan encapsulated the event, Richard Goering observed the event, and Steve Leibson abstracted the event.
I was also there on February 29th in Santa Clara, but rather than re-invent the wheel and provide redundant commentary, I’ve taken my notes from the evening and used them to create a Word Cloud. [see below]
If you study it carefully, you’ll see it pretty much sums up the emphasis of the panel discussion: Synopsys’ Aart de Geus, Mentor’s Wally Rhines, Cadence’s Lip-bu Tan, ARM’s Simon Segars, and Gradient’s Ed Cheng in conversation with Ed Sperling, exchanging ideas about Different Problems in EDA: Tools, Power, IP, Memory, Integration, Systems, Hardware, Software, Money and Innovation.
Now let’s look at the Word Cloud without any of the names, just the issues that swirled about in the conversation on February 29th.
When it comes to Westerns, nothing satisfies more than the one about long-time compadres getting together to do one last ride, one last round up, to take one last stand.
It satisfies, because it’s been years in the making and involves all aspects of the genre – long, lonely shots of distant horizons, fading references to the “exploration and settlement of previously untamed frontiers”, and a rich narrative of “rugged, self-sufficient individuals taming a savage wilderness with common sense and direct action.”
This particular type of Western also satisfies, because we know the players well – their faces, their mannerisms, how many notches they’ve got in their gun belts, and whether they normally ride alone or in a posse.
You are registered as: [_EMAIL_].
CafeNews is a service for EDA professionals. EDACafe.com respects your online time and Internet privacy. Edit or Change my newsletter's profile details. Unsubscribe me from this newsletter.
Copyright © 2015, Internet Business Systems, Inc. — 595 Millich Dr., Suite 210 Campbell, CA 95008 — +1 (408) 850-9202 — All rights reserved.