May 21st, 2015
Portable Stimulus Layer 2: Test Scheduling
May 20, 2015 by Tom Anderson, VP of Marketing
Last week, we continued our series of posts on the topic of “portable stimulus” as defined by Accellera’s Portable Stimulus Working Group (PSWG) and the standard they are working to define. We should say “we are working to define” since Breker is very much a part of the effort and is providing our many years of experience in this area to develop the best possible industry solution. As a reminder, we at Breker split the definition of a standard for portable stimulus into three parts: defining the tests using abstract primitive operations, scheduling the tests across multiple threads and multiple processors, and randomizing the control flow to verify the full range of realistic use-case scenarios.
Our most recent post dealt with the first layer: defining abstract tests using primitive operations and other elements within a base-class library, with access defined by a simple application programming interface (API). This week we consider the second layer: scheduling of tests and resources. If a verification engineer is writing a directed test for a single-processor SoC using the API calls from the first layer, then little of the second layer may apply. However, as we have discussed before, there is a clear trend of SoC designs moving to multi-processor designs with complex memory and cache subsystems and a rich variety of I/O protocols. These chips require automated test generation and the features provided by the test scheduling layer.
Python is making inroads in the EDA landscape, but is all the hype justified? Do the productivity benefits of a dynamic language translate to gains for real-world development for ASIC and FPGA designs? Chris Higgs of Potential Ventures will be onsite at DAC to share his experiences using Python and Aldec Riviera-PRO to take products from idea to production quickly.
Chris recently wrote a Guest Blog on the topic, visit the Aldec Design Verification Blog to learn more.
Using an MMU
May 20, 2015 by Colin Walls
Many microprocessors and microcontrollers incorporate a memory management unit (MMU) or have one available as an option. Equally, there are some devices that have no MMU support and many systems are built without one anyway. Having met some engineers recently, who could not conceive of the idea of no MMU, clarification may be necessary …
You may remember the Oski Technology Live Verification Challenge in 2012, where during the 72 hours of DAC, Oski verification engineer Chirag Agarwal formally verified a well-simulated design from NVIDIA, sight unseen, live and on camera, and found 4 corner case bugs. The challenge results exceeded everyone’s expectations, and inspired other companies to do more with formal in their verification flow. See the Live Oski Verification Challenge, and a blog recap and six-minute video, here.
Ladies and gentlemen it’s that time of the year again, DAC is less than three weeks away! I will be in San Francisco to provide daily updates of all the major news from the Moscone Center for those of you who won’t be attending, so you won’t miss out on anything from the three day exhibition. The ARM Connected Community is the place to be to find out about DAC news, photos, videos, partner announcements and gossip from the show floor throughout the event! In this blog I’ll give you a flavour of what DAC is all about as well as highlighting how ARM is engaging with partners in workshops, panels and poster sessions. Here is a link to the full list of ARM presentations and panels at DAC.
Well, the short answer to that is, “Awesome”. Perhaps, as the product manager of a simulation tool, I’m a little biased. Not to discount the challenges that FPGA design teams face on daily basis, particularly with device complexities now going through the roof.
There was a time, not so long ago, when using a single FPGA device from one vendor was not so uncommon and simulation and verification were quite interchangeable terms. However in recent years, with the development of more complex FPGAs and an even more complex design process involving the use of IPs, VIPs and third party models , the need for vendor agnostic tools for simulation and verification has become more evident.
Experience the DVContinuum
May 15, 2015 by Oliver Bell
What’s the DVContinuum?
For more than 25 years, DVCon is the premier conference to discuss challenges and achievements for Functional Design and Verification of Electronic Systems and Integrated Circuits. The DVContinuum includes the well-established DVCon United States in March, augmented with DVCon India in September and DVCon Europe in November (Munich, Nov 11 – 12, 2015).
For each region, DVCon provides a well-chosen mixture of technical paper sessions, tutorials, key notes, posters and exhibits. Sponsored by Accellera Systems Initiative, DVCon attendees get access to the latest information on various Accellera Standards and its application for system-level design, modelling and verification (including UVM, SystemC, SystemVerilog, IP-XACT and many more). The topics include system-level virtual prototyping, IP reuse, design automation, mixed-signal design, low power design and verification. Facilitating DVCon not only in the US but also in Asia and Europe allow networking and discussions in a much broader audience and expand DVCon’s value to wider community than those only who have the opportunity to travel to the US.
If you like to share your experience with the DVContinuum, submit your paper: DVCon Europe deadlines are May 11th for your draft paper and June 1st for your Tutorial submission. More info: http://dvcon-europe.org (India: http://dvcon-india.org/ US: http://dvcon.org/ )
The DVContinuum Anno 2015 – a Historic Perspective
As DVCon attendee, you will hear a lot about “shift left” and early verification of complex systems. This is not a new concept at all, even it may look like today. A very epic example for a historic shift left had been called out by John F Kennedy in May 1961: “I believe that this nation should commit itself to achieving the goal, before this decade is out, of landing a man on the moon and returning him safely to the earth.” At that time, the required technologies and procedures for a moon landing did not even exist.
You are registered as: [_EMAIL_].
CafeNews is a service for EDA professionals. EDACafe.com respects your online time and Internet privacy. Edit or Change my newsletter's profile details. Unsubscribe me from this newsletter.
Copyright © 2017, Internet Business Systems, Inc. — 595 Millich Dr., Suite 216 Campbell, CA 95008 — +1 (408)-337-6870 — All rights reserved.