EDACafe Weekly Review July 19th, 2012

I had the pleasure of speaking with Pranav Ashar, CTO at Real Intent, in the recorded video below, about how verification complexity is changing in new designs and how that is impacting design sign-off.

Dr. Ashar makes it clear scale complexity is not going away.  High-end SOCs today, easily go beyond 100M logic gates and we will see further CMOS silicon technology-shrinks, so bigger designs are forthcoming.  With the adoption of the SOC paradigm however, chips have evolved into true systems with diverse components integrated together into one design.

The elephant in the in the room that design teams are now realizing, is that the tremendous effort to create designs with aggressive performance and power goals has consequences for verification.   There are now first-order requirements that are not met by the nominal functional verification and timing analysis flows.

 

This week, Accellera Systems Initiative is announcing a new version of its SystemC library, Version 2.3 to be exact. There hasn’t been a new version since way back in 2005 with Version 2.1 (albeit 2.2, a bug-fix release, was published in 2006), so this is the culmination of a lot of hard work.

I spoke by phone with Accellera Systems Initiative Language Working Group Chair David Black, Senior Member of Technical Staff at Doulos, on July 17th.

Black explained, “The purpose of Version 2.3 is to reflect the latest version of IEEE Standard 1666 – to fundamentally demonstrate new features introduced into the SystemC standard, which includes TLM 2.0, previously an OSCI-only standard and now part of the IEEE standard. Interested parties can download the SystemC 2.3 library from the Accellera Systems Initiative website. This download includes several bug fixes, the latest TLM 2.0 and new SystemC features”

I asked Black who has participated in this work, and how often they meet. He said, “The Language Working Group of Accellera Systems Initiative includes all of the major EDA vendors – Cadence, Mentor, Synopsys, and Forte – and service providers such as Doulos and Circuit Sutra – and various members of the industry such as Intel, TI and STMicro, with everyone contributing a perspective.

“I am the Co-Chair of the SystemC Language Working Group along with Andy Goodrich [Forte Design Systems] and took over my position from Mike Meredith [also with Forte]. Key contributors also include Tor Jeremiassen [TI], John Aynsley and Alan Fitch [Doulos], Bishnupriya Bhattacharya [Cadence],  Jerome Cornet [STMicroelectronics],  Dr. Torsten Maehne [UPMC], Pat Sheridan and Bart Vanthournout [Synopsys], and Philipp Hartmann [OFFIS], along with many others.

MathWorks: the elephant in the room
July 18, 2012  by Peggy Aycinena

 

To get to MathWorks’ corporate headquarters outside Boston, take the Red Line to the Orange Line to Back Bay Station. Take the Commuter Rail to Natick, cross the bridge over the tracks, walk north along leafy Walnut Street for a mile and a quarter, turn left onto Route 9, and cross the grass to Apple Hill Drive. Turn left into the parking lot of the company’s campus, pick your way through the construction going on there, and look for the main reception building across from the big parking structure.

If you do all of this, and it’s 90+ degrees with 60% humidity, you’ll be totally drenched by the time you walk into the cool of the MathWorks headquarters. But no worries; the very nice person at the reception desk will send you down the hall to the closest break room where you can get a tall drink from the beverage dispenser and bring it back to the reception area to rest, recuperate, and prepare for your meeting with Ken Karnofsky.

Okay, two points of interest here: a) MathWorks is different. It’s headquartered in a residential neighborhood, not a commercial park; and b) the welcome is relaxed and not the high-pressure stuff of Silicon Valley.

Two additional points of interest: c) MathWorks is expanding. They’ve got 2400 employees currently, with an additional 200 job openings! Their Natick campus may offer a calm retreat from a humid Massachusetts afternoon, but it’s not a calm retreat from the world because when you’re there, MathWorks feels to be at the center of the world.

And d) MathWorks is definitely an EDA company, even though they don’t belong to EDAC and they don’t exhibit at DAC (although they have exhibited in the past). If you design chips, MathWorks’ MATLAB and Simulink is the gateway into your design. When it comes to EDA, MathWorks is most definitely the elephant in the room.

MIT: towards the 1000-core processor
July 17, 2012  by Peggy Aycinena

 

MIT is a disorienting place, particularly Stata Center, the home of EECS. There are no straight lines in the building and nothing appears plumb. Architect Frank Gehry, it seems, wanted his design to disturb and overwhelm and there he has succeeded, particularly when it rains: The building leaks. But does the building also stimulate? Again, Gehry has succeeded: The building hums with energy.

On a sunny day in July, the place is crawling with people. Students of various ages, genders, and nationalities wander by chatting in their t-shirts and flip flops, professors share bag lunches with their children in shady corners of the labyrinthine lobby, the line at the deli counter queues around in a disorderly sort of meander, while people in suits mingle with the flip-flop crowd in and under staircases that wander up and off into brick-lined oblivion.

Stata is part intellectual Grand Central Station and part Winchester Mystery House, enticing tourists and visiting scholars alike to wander in off the ponderous corporate streets of Cambridge.

EECS Professor Srini Devadas has an office on the 8th floor of Stata. When we sat down to chat there on Monday, July 9th, he started with an enthusiastic endorsement of MIT’s most famous building.

AMIQ


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