EDACafe Weekly Review June 18th, 2015

7 things I learned at 52DAC
June 18, 2015  by Neil Parris

Last week I attended the Design Automation Conference as an intrepid reporter to put my ear to the ground and take note of what is happening in the industry. I wrote some daily review blogs of my time on the show floor (which can be seen here, Day 1, Day 2, Day 3) but I have come up with some talking points from the conference. These are the topics that I found got most air time both in the booths and in the many speeches, presentations and panel discussions across the week. Let me know what you think about them in the comments section below.

Relentless collaboration

On Tuesday morning the VP of Samsung Electronics Foundries gave an insightful presentation on their advancements over the past 12 months and their vision for the foreseeable future. His words carry an extra amount of weight when you consider that in 2014 he promised 14nm silicon in a year’s time and was able to deliver on his word. It was not done in a silo however, and the phrase he used of “relentless collaboration” between EDA, IP companies and foundries is absolutely crucial to marching on with the progress he outlined, of seeing silicon for 10nm in 2016. The other key point he made was that each foundry process must be aligned to and optimized for the target segment. For example reducing the process node for server density and mobile, but there is still plenty of innovation at higher nodes for automotive, wearable and of course IoT. The same breakfast session showed proof of what can happen when partners collaborate. ARM®, Synopsys and Samsung managed to implement a quad-core Cortex®-A53 processor design with CoreLink™ CCN-502 designed for networking on a 14nm LPP process in a timescale of just four weeks.

Please Help Us Choose Our Next TrekApp
June 17, 2015  by Tom Anderson, VP of Marketing

As we have discussed before, we have followed the lead of other EDA vendors by packaging aspects of our advanced verification technologies into pushbutton applications (apps). The first in this product line, our Cache Coherency TrekApp, has been very popular since its introduction last year. As we have covered in depth, this is due in part to the trend of large chips becoming multiprocessor SoCs with multi-level caches. The sudden escalation of cache coherency verification from the CPU developer to the system integrator created strong demand for our nicely bundled solution.

There are many other trends ongoing and emerging in the SoC industry, and we have a long list of ideas for possible TrekApps to help address the challenges that are arising. We would like your help in prioritizing our development efforts. We have established a survey listing ten TrekApps under consideration. Please simply check off the ones of most interest to you by midnight Pacific time on June 30. All submissions will be entered into a drawing for a $50 Amazon.com gift card.

AMP vs SMP
June 16, 2015  by Colin Walls

It is becoming common for embedded designs to incorporate more than one CPU – maybe multiple cores on a chip or multiple chips on a board or any combination of these. Indeed, it has been suggested that it will soon be the norm to build systems that way.

The use of multiple cores has spawned various technologies and, of course, much terminology and jargon. When new technical terms and acronyms appear, there is inevitable misuse and misunderstanding. This seems to be the case with AMP and SMP, so maybe I can set the record straight …

S2C: FPGA Base prototyping- Download white paper


You are registered as: [_EMAIL_].

CafeNews is a service for EDA professionals. EDACafe.com respects your online time and Internet privacy. Edit or Change my newsletter's profile details. Unsubscribe me from this newsletter.

Copyright © 2017, Internet Business Systems, Inc. — 25 North 14th Steet, Suite 710 San Jose, CA 95112 — +1 (408) 882-6554 — All rights reserved.