August 18th, 2016
As of August 17th, when they posted financial results for Q3_2016, Synopsys is reporting somewhere in the neighborhood of $1 billion in cash and cash equivalents. As prudent as it may be to save for a rainy day, here’s something a bit more creative the company could do with a portion of that cash: Buy OneSpin.
Why? Because OneSpin offers something that Synopsys doesn’t have – a market-leading position in formal verification. OneSpin would bring that to Synopsys, along with a strong, well-established track record and proven customer engagements across European, North American and Asian markets.
Why Portable Stimulus Must Be Bidirectional
August 18, 2016 by Tom Anderson, VP of Marketing
When we first began offering our Trek family of products for what’s now known as portable stimulus, we talked a lot about vertical and horizontal reuse. Vertical reuse means that you can create a scenario model for individual IP blocks and generate test cases to run in their UVM testbenches, then move up to clusters and subsystems. The IP models can simply be plugged together to form a higher-level model from which appropriate higher-level test cases can be generated.
At the full-SoC level, you can generate C test cases that run on your embedded processors. Horizontal reuse is the ability to move from simulation to hardware (acceleration/emulation, FPGA prototypes, and silicon) while generating appropriate tests for these platforms from the same SoC scenario model. We generally described both forms of reuse in a unidirectional flow. However, bidirectionality is very valuable and, we believe, essential for portable stimulus. Let’s cover that topic in today’s blog post.
This is Part 1 of a 5-part discussion of the International Workshop on Design Automation for Cyber-Physical Systems co-located with the Design Automation Conference in Austin in June. Attending this all-day event on Sunday, June 5th, required a commitment of 9 hours and a $200 registration fee, albeit it came with a generous box lunch.
Over the course of the day, 10 speakers expounded on everything from complexity to reliability, from resilience to resource management, from smart buildings to smart grids to smart cars, and threw in a large dollop, as well, of how to deal with those miscreants among us who see opportunities in the emerging world of CPS to do small, medium, and large amounts of harm to our fellow humans and institutions.
Now it’s true, the thought leaders who spoke at CPSDA were consistently articulate, intelligent and well-informed. Nonetheless – even after 9 hours of intense listening, and quite a bit of caffeine – I was still not exactly sure what a cyber-physical system is. So let’s be creative and make up our own definition.
Today’s article is authored by Zach Nelson, Aldec FAE Intern. Zach is a Field Application Engineer Intern with Aldec, working in tandem with his fellow interns to develop hardware specific applications. He is set to graduate with a B.S. in Electrical Engineering from University of Nevada, Las Vegas in 2017. His field interests include ASIC Design & Solid State Electronics.
It’s time for Universities to say goodbye to their outdated FPGA boards and introduce the Xilinx® Zynq™ chip. The Zynq chip is a device which combines an FPGA fabric with a processing unit. The Zynq chip is very similar to other FPGA devices, but it does have a few key advantages and features that can enhance your designs and increase its capabilities.
What can Zynq do?
The Zynq chip has applications in the design fields related to:
- Digital Design
- Embedded Systems
- Factory Automation
- Algorithm Implementations
- Signal Processing
- Video/Image Processing
The Programmable-Logic can be used in isolation of the processor which allows it to be used like a general FPGA device which can help support the topics covered in any VHDL/Verilog class as well as Digital Design. It is much easier to facilitate growth and learning in a project-based curiculum when you have a device such as the Zynq to interface with.
Today’s article is authored by Brandon Wade, Aldec FAE Intern. Brandon is currently working on his B.S. in computer engineering from the University of Nevada, Las Vegas and is set to graduate in 2017. His interests include processor architectures, and the logic of these hardware designs. As a field application engineer intern, Brandon has worked extensively with Aldec’s own simulation software such as Active-HDL and Riviera-PRO.
When part of a team, your group can become more capable than a single individual, but only if your team can work together and communicate effectively. Having members of a group talk over each other leads to nothing but a cacophony, and nothing gets done. For this reason protocols need to be established, such as letting others speak without interruption, or facing those you are addressing. The same is necessary with electronics, especially with system on chip (SoC) designs.
The protocol used by many SoC today is AXI, or Advanced eXtensible Interface, and is part of the ARM Advanced Microcontroller Bus Architecture (AMBA) specification. It is especially prevalent in Xilinx’s Zynq devices, providing the interface between the processing system and programmable logic sections of the chip.
Shared code in embedded systems
August 15, 2016 by Colin Walls
A constant challenge I have found, when teaching or mentoring people, is to avoid making assumptions about what they know. I have found that it is so easy to assume that, because something is obvious to me, it is clearly apparent to everyone else. On numerous occasions I have discovered that this not to be the case. Of course, the best response to this realization is not to treat everyone else as stupid, but try to explain something clearly and then listen to the echo back of the explanation.
In developing software – embedded software in particular – there are certain things that are fundamental, particularly around the conservation of resources. More than once I have been surprised by engineers’ inability to focus on this issue …
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