EDACafe Weekly Review March 12th, 2015

Last week I attended the Design and Verification Conference in San Jose.  It had been six years since my last visit to the conference.  Before then, I had attended five years in a row, so it was interesting to see what had changed in the industry.  I focused on test bench topics, so this blog records my impressions in that area.

First, my favorite paper was “Lies, Damned Lies, and Coverage” by Mark Litterick of Verilab, which won an Honorable Mention in the Best Paper category.  Mark explained common shortcomings of coverage models implemented as SystemVerilog covergroups.  For example, because a covergroup has its own sampling event, that may or may not be appropriate for the design.  If you sample when a value change does not matter for the design, the covergroup has counted a value as covered when in fact it really isn’t.  In the slides, Mark’s descriptions of common errors were pithy and, like any good observation, obvious only in retrospect.  More interestingly, he proposed correlating coverage events via the UCIS (Unified Coverage Interoperability Standard) to verify that they have the expected relationships.  For example, a particular covergroup bin count might be expected to be the same as the pass count of some cover property (in SystemVerilog Assertions) somewhere else, or perhaps as much as some block count in code coverage.  It struck me that some aspects of this must be verifiable using formal analysis. You can read the entire paper here and see the presentation slides here.

I was also impressed by the use of the C language in verification — not SystemC, but old-fashioned C itself.  Harry Foster of Mentor Graphics shared some results of his Verification Survey, and there were only two languages whose use had increased from year-to-year: SystemVerilog and C.  For example, there was a Cypress paper by David Crutchfield et al where configuration files were processed in C.  Why is this, I wondered?  Perhaps because SystemVerilog makes it easy via the Direct Programming Interface (DPI): you can call SystemVerilog functions from C and vice-versa.  Also, a lot of people know C.  I imagine if there were a Python DPI or Perl DPI, people would use those a lot as well!

 

Given how much press is being heaped onto the whole wearable/IoT fad, it was refreshing to hear somebody speak in no-nonsense terms about one way to make it all work. Tuesday morning at Wearables TechCon in Santa Clara, an incredibly poised Rutgers undergrad named Victor Kaiser-Pendergrast gave a one-hour talk exhibiting a specific use case involving both Google Glass and Android Wear [your not-Apple watch].

The motivation for his demo was to highlight the fact that although some apps are perfectly suited to Google Glass [e.g., navigation] and others are perfectly suited to Android Wear [e.g., list selection], there are a host of apps which are best implemented using both technologies.

Shooting a clay target, for example: The target is displayed on Glass and you aim by moving your head. “But I don’t want to smash Glass on my face to fire,” Kaiser-Pendergrast said, “because that dislodges Glass just enough to cause a miss.” For shooting clay pigeons, therefore, it’s better to tap or swipe Wear on your wrist to guarantee an accurate hit on the target.

From that demo, Kaiser-Pendergrast moved to the problem at the core of his talk: Using Google Glass, Android Wear,  and as it turns out, an Android Handset to order a cheese sandwich from a local deli.

Decoding Formal Club Unlocks Some Mysteries
March 10, 2015  by Tom Anderson, VP of Marketing

Last May, I published two blog posts on the presentations made at a “Decoding Formal Club” event hosted by the smart folks from Oski Technology at the Computer History Museum in Mountain View. With everything else going on, I didn’t manage to make it to another of their regular meetings until last week. The first event of 2015 was very interesting, so again I’m returning to the popular topic of formal analysis and playing reporter. The line between media and blogging is rather thin these days anyway.

This edition of Decoding Formal featured three talks, one an end-user case study and the other two  instructional in nature from well-known formal experts. I found all three worthwhile and will do my best to communicate some of the main points made. I also have to mention the final presentation, more a performance than a talk, by the inimitable and irrepressible Clifford Stoll. Lately he’s been manufacturing and selling Klein bottles, which you may remember from a geometry teacher trying to mess with your mind.

Screen shot 2015-03-10 at 11.37.44 AMIf you’re a board engineer, are you encountering high-speed issues? What are they?

One that’s garnering some thinking and observer attention is signal integrity for high(er) speed board designs.

With most all designs running at 10 Gbps (more mainstream these days), and approaching 25 Gbps, current measurement and verification of S-parameters seems to be an increasing concern.

At DesignCon, SI authority Erig Bogatin and Industry observer Max Maxfield discussed different aspects of this problem with AtaiTec CEO Ching-Chao Huang.

 

Hello all I’m Neil Parris, a senior product manager at ARM. I’ll be blogging from time to time about certain issues surrounding EDA and IP integration in particular. I hope to provide some valuable insight into the sometimes murky world of SoC development. Please enjoy the content and don’t hesitate to leave comments or ask questions. My blogging debut on this platform comes in the form of an interview, as I sat down and chatted to David Murray. If you don’t know him, David joined ARM last year as part of the Duolog acquisition and is working as an IP Tooling Architect. He is incredibly enthusiastic and articulate so it is always a pleasure to speak with him.

Celebrating Lives: Martin Vlach & Jiri Vlach
March 9, 2015  by Peggy Aycinena

 

Dr. Martin Vlach will be hosting a Celebration of Life to honor the life of his late father, Dr. Jiri Vlach, on Saturday, March 14th. Both father and son are uniquely renowned for their contributions to various technologies at the center of semiconductor design.

Interestingly, when fathers are accomplished, the sons often suffer, fearing their own accomplishments may not match the track records laid down by their father before them. When exceptions occur they are well worth noting, and certainly that is the case with Martin Vlach, Mentor Graphic’s Chief Technologist for Analog-Mixed Signal, and his father, Jiri Vlach, until his passing last month, a Distinguished Professor Emeritus of Electrical and Computer Engineering at University of Waterloo, Ontario, Canada.

CALYPTO: Launch Catapult 8
CAD/SW Engineer


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