EDACafe Weekly Review July 12th, 2012

In this video interview, I talk about the two recent press announcements that just came out about new product releases and growing business momentum, and the fun we were having at the Real Intent booth at DAC in San Francisco, June 4-6.

Here you can see the Foosball table in action:


It may be summertime, but the folks in the Verification world are clearly not taking any holidays.

This week, four different verification-related news announcements arrived, presenting an interesting set of positive mid-year perspectives: Breker’s new round of funding, EVE and Synopsys’ co-emulation success, Cadence’s beefed-up PCIe VIP, and a new co-simulation interface from Aldec and Agilent. Good news on all fronts and now these folks should take a vacation!

EDA: 7 Grand Challenges
July 11, 2012  by Peggy Aycinena


The concept of a Grand Challenge is an established one in engineering, so here in 2012 what are the Grand Challenges in EDA? Let’s go out on a limb and name a few candidates:

No.1) Low power: This is the critical problem here in the era of mobile everything. If you can’t guarantee low power for your device, it’s going to go dark way too soon and be way too hot in the meanwhile. Great challenges remain in perfecting the tools to make this all happen.

No.2) Formal verification: There just has to be a way to guarantee that what we meant to design, has been designed and then manufactured. Isn’t that the goal of formal verification, and isn’t it true that we’re not quite there yet?

No.3) 3D-ICs: In the last several years, this one’s gotten a lot of attention, but it appears that there’s still a lot of work to do – at least on the logic side of the equation. Clearly more tools are needed.

BDA: Two different definitions at DAC
July 10, 2012  by Peggy Aycinena


It’s stranger than fiction, but there are actually two different entities at DAC that bear the name BDA, and they’re both acronyms.

One is a company very familiar to the EDA space, Berkeley Design Automation. As you know, President & CEO Ravi Subramanian has just been elected to a second term as a member of the Board of Directors of EDAC.

Subramanian’s BDA is in the news again this week because they just announced that ATopTech, also an EDA company, is now using BDA’s Analog FastSpice to “enhance the accuracy of the timing analysis in [ATopTech’s] Aprisa P&R product for designs at advanced process technology nodes such as 28nm and 20nm..”

So what is the other BDA at DAC? It’s Biological Design Automation. The International Workshop on Biological Design Automation figured large on Sunday and Monday, June 3rd and 4th, in San Francisco where it was again co-located with the Design Automation Conference, as it has been for several years.

Call for Abstracts is now open for DesignCon 2013
July 10, 2012  by Hélène Thibiéroz

As a chair(wo)man for the AMS track at DesignCon (yes I know, you heard it before :) ), I just want to inform you that the call for abstracts is now open for DesignCon 2013:


You have until August 17,2012 to submit your abstract. In order to get innovative content, our AMS technical committee selected a large range of topics representative of actual and upcoming challenges faced by AMS engineers (I have included this list below). You can submit your abstract using the above link.

Feel free to contact me anytime if you have any questions, we look forward to reviewing your abstracts.

You can find some related information to last year tutorial and event at:



I am also working on a tutorial and panel focusing on Mixed Signal Verification, more to come later…



Analog, RF, and Mixed-Signal Design and Verification sample topics

Design & verification methodologies

Simulation algorithms and techniques

Mixed-signal behavioral modeling approaches

Verilog-A, Verilog-AMS, VHDL-AMS, SystemVerilog, SystemC-AMS, etc.

Mixed-domain design and verification solutions

MEMS, electro-optics, mechatronics, etc.

Mixed-domain/mixed-language verification strategies

Analog and RF IP: selection, integration, and modeling

Coverage, metrics, and closure management

Power distribution & management

Yield analysis, Monte Carlo methods, and optimization approaches

On-chip inductors: design and modeling

RLCK extraction: post-layout flows and strategies

Noise analysis and prediction: substrate, spurious, random

Variability effects and statistical analyses

Article source: Cosmic Circuits

Cosmic Circuits, a leading provider of differentiated Analog, Mixed-Signal and Connectivity IP cores, today announced the silicon availability of its MIPI M-PHY solution in 28nm.

Cosmic Circuits offers a broad portfolio of differentiated Analog IP cores in nanometer technology nodes covering Data-Converters, Analog-Front-End platforms for Wireless and Audio, Power-Management, Clocking and MIPI Interfaces.

Cosmic Circuits M-PHY solution supports both the HS-G1 (1.5Gbps) and HS-G2 (3Gbps) modes and is available in multiple process technologies ranging from 85nm to 28nm. The silicon has been characterized across supply, temperature and process corners and detailed characterization reports will be available very soon. Here is a video showcasing Cosmic Circuits validation platform and methodology for the MIPI M-PHY:

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