August 9th, 2012
This article is an update to Lisa Pipers original posting from April 2011: X-verification: Conquering the “Unknown”
SoCs today are highly integrated, employing many disparate types of IP, running at different clock rates with different power requirements. Understanding the new failure modes that arise from confluences of all these complications, as well as how to prevent them and achieve sign-off, is important. While the issue of handling “X’s” in verification has always been there, it has become more exasperated by low power applications that routinely turn off sections of chips, generating “unknowns”.
Lisa introduces the topic of X-Verification in her DVCon 2012 video interview:
Ali Iranmanesh is a busy man. He continues to head up the Silicon Valley Institute of Technology, the school he founded in 1997, and continues to lead ISQED, the conference he founded in 1999. Now he is also leading ASQED, the Asia-based spin-off of ISQED Iranmanesh founded in Malaysia.
I caught up with Ali in early August by phone. He was in Silicon Valley and had just returned from ASQED 2012 in Penang, Malaysia.
WWJD: What prompted you to start ASQED?
Ali Iranmanesh: It was a natural extension of ISQED, which I started 14 years ago. I decided to keep ISQED in Silicon Valley, and to create other conferences for different regions.
WWJD: Remind me how many ASQED’s have taken place.
Ali Iranmanesh: This is our fourth year, with the conference alternating between Kuala Lumpur and Penang in Malaysia. Our next event is scheduled for August 26th to 28th in Penang.
WWJD: Malaysia seems an unusual destination for a conference on design.
Ali Iranmanesh: Historically, there has been a lot of manufacturing in Malaysia, but not so much design. I’ve been working with the several government entities there, helping them to move up the value chain through training, and was able to implement the conference as part of that process. Now for the past few years, there has been design going on in Malaysia – the conference has done a great job helping with that.
If you read my blog or other EDA related blogs, you probably have already figured out that verification, specifically for mixed-signal designs, is getting increasingly complex. Different variables have to be taken in consideration: complexity of your design environment or topology, high-volume of regression runs, simulation speed are just a few of those . The verification methodology has also to support multiple languages, and work with different netlist formats available across the industry. As such, there is a crucial need for an integrated mixed-signal verification environment that focuses on functionality, reliability, and performance.
Well, today is your lucky day, Synopsys has such a tool . CustomExplorer™ Ultra (CXU), is a GUI- and netlist-based verification platform that helps automate Verification regression tests without manually creating different configuration files or scripts.
Medals: Why we love them
August 8, 2012 by Peggy Aycinena
Everybody loves to get medals because everybody loves to be best at something: Swimming, Diving, Rowing, Running, Jumping, Hurdling, Riding, Kicking, Dunking, Punching, Throwing, Serving, Digging, Batting, Vaulting, Balancing, Leaping, Cycling, Dancing, Singing, Strumming, Humming, or Whistling.
In the same way, everybody loves to get awards because it also means they’re be best at doing something: Starting, Founding, Investing, Inventing, Creating, Building, Programming, Designing, Testing, Manufacturing, Assembling, Integrating, Packaging, Selling, Leading, Teaching, or Winning.
Yes, it’s true: Everybody wants to be best at something, everybody wants to get a medal or an award, and yet it’s also true that not everybody can. Not everybody can be best, because the equation simply doesn’t allow for it.
And for those who cannot win awards or medals, they have two choices:
It is the Sunday night pre-reception before DAC; it is fairly crowded and most of the bigwigs of DAC are there, and umm so am I. As I walk around in my trademark WHITE JACKET, fraternizing with old friends and meeting new people, I run into Aart, that’s Aart de Geus, CEO of Synopsys. (I guess I now say, CO-CEO).
He is his usual charming self. I asked him about his thoughts on the column I wrote about our chance 30-minute talk at the last DAC. He says, “Who the heck are you”? Well not exactly. After a few reminder nudges he said, “ah yes I do. “I thought your article about me was fair and balanced”. I said like FOX NEWS and he noticeably chuckled. After some light banter about the column, to my amazement, he followed with, “would you like to do it again”? I choked slightly in shock and answered, of course. This was 8 at night, the Miami Heat (my team) were on TV in the playoffs playing at that moment, and I knew the next many hours would be spent preparing for this privileged opportunity. He asked me to meet him at the Synopsys booth and from there we walked the few blocks to the Marriott, chatting like I would with a new friend, so easy and nonchalant.
The walk was so casual, discussing little tidbits about our personal life. I think I learned more about the man during our walk than I did in the actual interview. For a guy running a BILLION DOLLAR PLUS company, he is about as casual and down to earth as you and I. The only difference (well at least speaking for myself): he has an IQ of about 500 points more than I have and a vision of reality hardly imaginable by most.
At DAC this year I had a lot of fun doing a live experiment to demonstrate some of the benefits and issues with concurrent design flows. I was at the Cadence Theatre doing a presentation called ‘Controlling the costs of SoC integration‘ and I decided to make the presentation more interactive by creating a design team and seeing some of the effects of getting this team to work concurrently. We demonstrated how a little ‘twist’ caused a big upset for to team deliveries!
The topic I introduced first was how system design flows are now highly concurrent. In the production of a system within a very tight timescale, it would be normal to have architecture definition, software development, virtual prototype development, RTL design and verification all happening at the same time, be it IP, sub-system or SoC level design. I represented this as a set of rotating, interacting cogs.
Article source: Kilopass Technologies
The world population hit 7 billion last fall, with a billion more expected in a dozen years. “Lifecare” represents an incredible opportunity for the semiconductor industry to promote health, energy conservation, safety and productivity. From smart city infrastructure to medical care advances, from sensors and controls to nanotechnology, what new EDA ecosystems will emerge to better model the real world? Panelists participating in the discussion “Is Lifecare the Next Killer App?” at the Design Automation Conference on June 4, 2012 addressed the question and their remarks are quite enlightening. Moderator Rick Merritt, Editor at large, Electronic Engineering Times led the discussion, which included Kristopher Ardis from Maxim Integrated Products, Fabrice Hoerner, from QUALCOMM Inc. and Greg Fawcett from Palo Alto Research Center.
Road to Where?
August 6, 2012 by Sherry Hess
Earlier this year, I posted a blog, Are You a Do’er?, which was inspired from my participation at the Business of Software Conference late in 2011. There was a wealth of content presented at that conference and of course it inspired another thought thread that now lends itself to a blog topic.
The theme… Road to Where? Are you, or I, or perhaps both of us, on a road to nowhere? Are we caught up in the innovation race to add more features and functionality to our software/hardware/whatever product that we lose sight of what’s important to the user base? This was the talk of a few folks at the conference, but one person in particular, Harvard Professor Clayton Christensen, argued in his talk (here is the video) that we need to shift our focus away from adding more and more features into what is already a well-functioning product and keeping up the innovation race with our competition, and instead figure out how to bridge the divide between consumption and non-consumption. Prof. Christensen, who is also quoted in the book, Mastering the Complex Sale by Jeff Thule, asks what can you do to pull in new users/customers that for whatever reason have not found their way to your offering (product/service)?
Now I imagine I have a few of you interested in debating this with me and thinking, “Hold on a minute Sherry, are you saying to forget about your current customers and simply focus on the ‘haves’ vs. the ‘have nots’?” Well, not at all! Prof. Christiansen goes on to explain that most customers today are bombarded with so much information about a product and service that we, by human nature, simplify it for sanity sake so that when it comes to a comparison of features/functionality, we are able – in a timely fashion – to reach a decision.
Jasper’s formal technology has advanced to the point that it can address a broad range of verification and design issues. With a strong foundation in fundamental proof technology and best-in-class capacity and performance, Jasper’s users now apply the tools and technology to address questions of connectivity, x-propagation, clock-glitch detection, protocol cache coherence, deadlock detection, property synthesis and more.
The added scope and breadth of use of Jasper’s tools and technology is leading users to demand a measurable and quantitative approach that will help correlate the results of formal proofs to verification closure, often expressed in terms of verification coverage. What is needed is a methodology that will correlate formal proof results with coverage. A second requirement is for a methodology that can integrate the coverage results from Jasper’s formal technology with other verification tools (simulation). A third requirement is the ability for Jasper tools to use external coverage data to address areas in the design that are not covered by other verification methodologies.
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