Shakeel Jeeawoody is VP of marketing at Blue Pearl. I enjoyed a long conversation with Shakeel at SAME Forum in France in October, and again at ARM TechCon in November. We completed the discussion by phone this week, starting with a brief profile of Blue Pearl and a discussion of FPGA versus ASIC design needs.
Per Jeeawoody, “Blue Pearl has been around since 2005, we’re located in Santa Clara, and our technology has all been developed in-house. Our underlying technology improves RTL analysis using symbolic simulation techniques and adapting them to our customers’ market requirements. We have competitors in the linting and clock-domain crossing [CDC] space, but not many that can generate SDC constraints and offer easy-to-use tools that run on Windows at an attractive price point to support FPGA designers.
“More FPGA designers today struggle with IP integration in their projects in the same way ASIC designers have in the past; if they don’t do the right level of analysis, there are reliability problems in the field. With that in mind, we focus on addressing emerging and major FPGA design issues – one we call Grey Cell Methodology, and we offer mode-based analysis to address issues associated with longest path analysis.
Last month, Lou Covey posted comments regarding a blog posted here about Esencia Technologies, the company that received Software Best-in-Show at ARM TechCon. He took issue with my suggestion that it was unclear why Esencia received the award.
Covey’s comments prompted my phone call with Karl Kaiser, VP of Engineering at Esencia, who explained: “EScala is a design platform that takes a C algorithm for things like MP3 encoders, and creates an IP block for the design – a reprogrammable core for the target architecture. EScala allows you to generate a core that fits your algorithm.
“At Esencia, we have provided a lot of ASIC design services and wanted to find a way to simplify the traditional RTL flow – architecting, partitioning, implementing, and writing the testbench. EScala is a result of that effort and is unlike anything else on the market.
December 4, 2012 by Jim Foley, Director of R&D, Real Intent
This is the second in our series on lint rules, where we discuss various coding issues and how to improve the quality of RTL designs. The lint rule for this month is OPEN_INPUT.
How many different ways can you express nothing? And do you mean the same thing each time?
It’s not as if Ascent Lint has a rule that will look for nothing and point out to you where nothing is discovered. There is a whole category of rules for this! Over 30 rules in the Omission category will point out nothing in various situations with the general expectation that there should be a coding element, but it is missing.
Not all nothings are necessarily the same, however. Consider these three module instantiations:
Over the last couple of weeks we’ve been exploring the concept of stale IP – what it is and what to do about it. I’ve gotten insights from two industry experts in IP (Harrison Beasley of GSA and Manoj Bhatnagar of Atrenta). I will wrap up my series on this topic with one final view – from IP provider, Warren Savage, founder and CEO of IPextreme. He will challenge the whole idea of stale IP in this interview.
Liz: Stale IP – what is it?
Warren: Frankly, I’ve been working in IP for seventeen years, with most of the world’s largest IP and chip companies, and I have never heard the term before. I think people who think about IP being “stale” may be confused about the difference between IP and code. IP is certainly code, but code is not necessarily IP. I have argued vociferously for years on this topic, particularly opposing those who would claim that IP is a service business (see an old blog post by me “Repeat after me: IP is Product Business…” http://blogs.ip-extreme.com/2009/07/test-page.html). I think this notion of “stale IP” is sort of a regurgitation of the idea that there are classes of IP. For me, IP is something that is reusable indefinitely and valuable as long as there is a market for it.
The world of EDA is about to change. The subtle signs are there for all to see, and the coming reality is so different to be scary to some. Thus better not to talk about it. The changes will include how ICs are designed, developed, and verified. They will involve designers, tools developers, and manufacturers, and force an integration that the EDA industry has not experienced so far.
I have followed with great interest the various press releases from TSMC, Cadence, Mentor, and Synopsys describing the work, and the progress, toward finalizing a commercial grade 20 nm process. It is interesting that the vast majority of the news is about TSMC. There is a perplexing lack of news from other foundries about their work on the 20 nm process. Thus the question: are they already done or are they lagging behind?
I tend toward the second explanation. Accustomed to moving from one processing node to the next with regularity, I believe that most commercial foundries have been caught by surprise by the increased difficulty that the 20 nm process holds. it is not just a matter of developing a cell library, or to create and calibrate a new nanolithography process.
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