EDACafe Weekly Review September 5th, 2013

For today’s SoCs, modern power management schemes affect how designs are reset (started). X management and reset analysis are interrelated because many of the X’s in simulation come from uninitialized flip-flops and, conversely, the pitfalls of X’s in simulation compromise the ability to arrive at a clear understanding of the resetability of a design.

In the video interview below, Pranav Ashar, CTO at Real Intent, points out how verification sign-off now must include analysis of reset and design initialization to ensure it is correct and optimal for various power modes in an SoC.

Fall Calendar Update: The pace quickens
September 5, 2013  by Peggy Aycinena

 

Okay, summer’s over, September has arrived, and it’s time to figure out where you’re going to go over the next few months, conference wise. Some events are imminent, but others are a ways out, giving you time to think about registering and attending. Some events are vendor neutral, while others are vendor specific, which doesn’t preclude a chance to learn stuff. Although this list is lengthy, it isn’t comprehensive.

* ITC 2013
International Test Conference
Anaheim – September 8-12

* IDF 2013
Intel Developers Forum
San Francisco – September 10-12

* SNUG Taiwan
Hsinchu – September 10-11

* CDNLive China 2013
Beijing – September 10

The demise of VHDL has been greatly exaggerated
September 5, 2013  by Michiel Ligthart

I don’t recall when it was the first time that I heard VHDL was a dying language, but for sure it was many years ago, maybe as far back as the late 1990s. Obviously the EDA futurists of then got it very wrong, and I was recently wondering if I could put a number on how wrong.

At Verific, as the premier provider of SystemVerilog and VHDL parsers to many  EDA, FPGA, and semiconductor companies, we do have some good insights in what our customers license from us and how they use it. Since its start, Verific has shipped just over 100 licenses. So I sat down and tallied the HDL languages companies obtained from Verific during that period. Here is the countdown

Article Source: Cadence Design Systems

25 years ago (1988) ECAD and SDA Systems merged to form Cadence Design Systems. At U.C. Berkeley Alberto Sangiovanni-Vincentelli played key roles in the formation of ECAD, SDA Systems, and Cadence, and in this video he explains how Cadence was started.

Herb Reiter: The three-legged stool of Technology Choices
September 5, 2013  by Peggy Aycinena

 

Herb Reiter, founder and president of eda2asic, has been in the semiconductor and EDA industry for 30+ years, including stints at Barcelona Design, Viewlogic, Synopsys, VLSI Technology, and National Semiconductor. In the last few years, Reiter’s work has focused on SOI, 2.5/3D ICs, and FinFET topics in semiconductor design and manufacturing. Straightforward enough, until you realize that these are significantly different ‘3D’ technologies, where ‘3D’ means different things to different people.

In a recent phone call, I asked Reiter to distinguish between what he calls the “three legs” of technology choices and to weigh in on which “leg” is most likely to succeed.

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Fully-depleted SOI …

Per Reiter, “The original technology was partially-depleted SOI, a fairly thin film of silicon on top of a thin insulating layer. IBM came up with the idea, because substrate capacitance was slowing their chips down. They realized if they put in the insulating layer, they wouldn’t have to worry about substrate capacitance, because the oxide layer would insulate things.

“The planar transistor gate cannot reach all of the electrons in an 80-nanometer channel, cannot fully control the flow, and causes what we called ‘body-effect’ and ‘kink-effect’ design challenges. That’s why partially-depleted SOI was not widely used. So fully-depleted silicon on insulator, FDSOI, was introduced. It only has about a 20-nanometer active film on top of the oxide layer. The gate is sitting on top of the active film and can control all of the electrons passing through the source/drain channel, which is why it’s called fully-depleted SOI.

If the EDA Industry Has Zombies, What about Vampires?
September 3, 2013  by Tom Anderson, VP of Marketing

In just a week, my last post has become the most-read since we launched The Breker Trekker blog. That’s fine with me; beneath the intentionally provocative title I had some serious observations on how the EDA industry has evolved over the last couple of decades. My thought for the week is “never underestimate the power of zombies to grab people’s interest.” Mentioning zombies make me think of vampires, since the two are so intertwined in popular culture. There are lots of articles on why we’re so fascinated with these two creatures, and what it means when one is more popular than the other.

I’ll bet that most of you are running ahead of me now and thinking, “Vampires? This must be Breker’s column about venture capitalists.” Indeed this is a post about investors and their role in the formation and fate of EDA companies. Sure, some venture capitalists (VCs) might be viewed as vampires or vultures. But in my personal experience I’ve seen a wide range of investors with very different motivations and methods of interacting with their startups, most of them quite positive.

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