March 5th, 2015
The Design and Verification Conference Silicon Valley was held this week. During Aart de Geus’ keynote, he shared how SoC verification is “shifting left”, so that debug starts earlier and results are delivered more quickly. He identified a number of key technologies that have made this possible:
- Static verification that uses a mix of specialized code analysis and formal technology which are must faster and more focused than traditional simulation
- New third generation of analysis engines
- Advancements in debug
Real Intent has also been talking about this new suite of technologies that improve the whole process of SoC verification. Pranav Ashar, CTO at Real Intent wrote about these in a blog posted on the EETimes web-site. Titled “Shifting Mindsets: Static Verification Transforms SoC Design at RT Level“, it introduces the idea of objective-driven verification:
We are at the dawn of a new age of digital verification for SoCs. A fundamental change is underway. We are moving away from a tool and technology approach — “I have a hammer, where are some nails?” — and toward a verification-objective mindset for design sign-off, such as “Does my design achieve reset in two cycles?”
Objective-driven verification at the RT level now is being accomplished using static-verification technologies. Static verification comprises deep semantic analysis (DSA) and formal methods. DSA is about understanding the purpose and intent of logic, flip-flops, state machines, etc. in a design, in the context of the verification objective being addressed. When this understanding is at the core of an EDA tool set, a major part of the sign-off process happens before the use or need of formal analysis.
DVCon: The Imitation Game
March 5, 2015 by Peggy Aycinena
What if I were to tell you that I attended a conference where people were really excited to be there, where the exhibit hall was filled with a crush of people making their way from booth to booth, talking with exhibitors and exchanging business cards madly. A conference where the South of the exhibit hall was dominated by Synopsys, the East by Cadence, and the West by Mentor, and where at the happiest hour, libations and snacks flowed freely in a sub-set of the booths and the whole exhibit hall became even more animated.
What if I told you the technical portion of the conference included a variety of content — touching at times on autos, wearables, the IoT, IP, standards, and verification — excellent panel discussions, well-attended poster sessions, detailed tutorials, and a keynote from the CEO of the largest company in the industry delivered to a packed, SRO ballroom full of designers, engineers, and engineering managers.
Finally, what if I told you the highly capable staff of MP Associates was running the whole thing with their usual aplomb, attending to details as diverse as registration, sound systems, lunch tickets, speaker logistics, and awards presentations.
In last week’s blog post on The Breker Treker we previewed this week’s Design and Verification Conference (DVCon) in San Jose, the leading industry event for verification professionals. We had a really good time there, finishing up just this afternoon. We always enjoy DVCon, but this week was even more fun than usual. We met attendees from an amazing range of companies designing SoCs, from simple microcontrollers to some of the largest FPGAs and custom chips on the planet.
Three aspects of the show really stood out: intense interest in cache coherency verification, considerable curiosity about the Accellera Portable Stimulus Working Group (PSWG), and the number of people who started the conversation with “I’ve heard good things about Breker from a colleague” or “I was told that I really need to check you out.” Let’s discuss what each of these trends means for the industry and speculate about the impact on Breker.
This weekend on March 7, there will be Holi celebrations throughout San Jose and Silicon Valley. In a celebration of spring that first started in India, young people gather to throw colored powders on each other, and often water is used to smear the colors as well.
Holi Festival at Stanford University Campus, sponsored by Asha for Education
I have taken part several times with friends who grew up in India. It is a lot fun and the food and sweets are excellent. One popular celebration will be in Milpitas on March 7. You can find all the details here.
Every engineer and technician is aware of Murphy’s Law: “Anything that can go wrong will go wrong”.
The law appears when your elegantly-sculpted hardware and artfully-styled software code bang up against the real world of transition delays and timing requirements.
Over time, designers and trouble-shooters develop a healthy respect for Mr. Murphy and begin to anticipate when he is looking over their shoulder, learning “best practices” for recurring design problems.
The toughest design problems to trouble-shoot are ones that fail intermittently. A hidden flaw seems to pop up randomly with no certain pattern or definable cause.
DesignCon, held at the Santa Clara Convention Center, is one of the biggest annual conference on product technologies, design methodologies, and EDA software, with a focus on system-on-chip design.
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