August 2nd, 2012
When it comes to wow factor, nothing outpaces the August 3rd announcement that Synopsys is going to acquire Taiwan-based SpringSoft. The announcement is astonishing for three reason:
1) Synopsys just announced the acquisition of Ciranova last week. True, the details of that deal were not released and Ciranova is not a ‘large’ company – still, two acquisitions by Synopsys in as many weeks is noteworthy.
2) SpringSoft is a publicly-traded company and therefore the details of the acquisition must be announced: Synopsys will be paying about $300 million for SpringSoft (net of cash acquired), which is a helluva lot of money …
3) … given that Synopsys has already executed another high-profile, high-priced acquisition of a publicly traded company earlier this year, buying Magma Design Automation for about $523 million (net of cash acquired).
When Eric Filseth took over as CEO at Ciranova in September 2007, he was already a seasoned EDA veteran having clocked in an accumulated 17 years at Cadence at that point. Now here in 2012, Ciranova has just been acquired by Synopsys and it would seem Filseth’s organization has fulfilled the vision he articulated 5 long years ago.
Per Filseth in 2007: “The problems in analog are very hard. In the digital world, everything is very, very automated, but in the analog world it just isn’t that way. It’s still mostly done by hand and the concept of IP as you consider it in digital – take the RTL and port it to this design or that process – is not there. In analog, it’s still a manual thing for PLLs, and amplifiers, and so on.
“There’s been so much focus on digital SoCs, and things like place and route, there’s been a lot less time spent on analog. Now digital design works fantastically well. You can get a junior engineer with only a couple years’ experience designing thousands of gates a day.
“Just think about it. Over the last 20 years, we’ve had 4 or 5 generations of digital architectures developed but in analog, people are still doing things the way they did it 15 or 20 years ago. Clearly there‘s an opportunity here, and Ciranova is well positioned to take advantage of that opportunity.”
Enough can’t be said about the power to educate based on experience. At this year’s DAC, a few of Jasper’s top users volunteered to give seminars on their best practices for using Jasper Formal technology. If you happened to miss DAC or did attend but didn’t get a chance to visit the Jasper booth, here’s your chance to view the on-line videos from ST, ARM, and NVIDIA on how they utilized Jasper Formal technology to get ahead in their designs.
ST: Low Power Verification and Optimization with Jasper Formal
ST Microelectronics talked about the verification challenges associated with sophisticated low-power designs, and ways those challenges are being addressed by Jasper’s power-aware formal verification technology. The seminar detailed how Jasper’s low-power verification solution applies to:
- Parsing CPF information to enable power-aware formal analysis
- X-propagation due to shutting down power
- Functional impact due to power-down
- Power-up state analysis
- Exploration of power-state
A Visit to Uniquify
August 1, 2012 by Dr. Russ Henke
Dear faithful blog reader: Please take a few minutes of your valuable time to read the July 26, 2012 article, “A Visit to Uniquify – Unique and Impressive.”
You may reach the new July 26 Commentary via two different paths:
(1) Returning to the front page of EDACafe.com, and scrolling down the front page, finding a box with a URL posted with a photo of yours truly, and clicking on the title in the box:
(2) By clicking here right now on the URL below to go directly to the article:
Verification is getting to be a more and more critical step in today IC designs. As more and more analog designs evolve into mixed-signal ones, verification methodologies and strategies need to be further refined and improved to address new challenges. While the verification of the logic part, mostly implemented in Verilog and VHDL, has gained momentum, the analog part suffers from not being supported by this language. To speed up the verification of the analog part (SPICE, Verilog-A(MS), VHDL-AMS), innovation is needed.
In our previous post, we talked about VerilogAMS, which is one approach. In this post, I wanted to talk about an other approach, Real Number Modeling, and highlight the efficient solution developed co-jointly by ST Ericsson and Synopsys, which is based on Synopsys CustomSim-VCS VHDL- Real Number flow. Using this flow, ST-E was able to boost simulation performance and increase verification coverage of their most complex AMS chips.
Both flows (VerilogAMS and Real Number Modeling) are fully supported by Synopsys.
Article source: ASQED
ASQED 2012 was held on July 10-11 at Penang, Malaysia.
The 4th Asia Symposium on Quality Electronic Design (ASQED 2012) was the fourth event organized by the International Society for Quality Electronic Design with technical sponsorship from several IEEE Societies. This event was sponsored and managed by SHRDC. ASQED emphasizes innovations and the latest developments in System and IC Design, MEMS & NEMS, Semiconductor Technology & Manufacturing, IC Packaging & PCB Technology, Test, and Bio & Nano Electronics.
ASQED Microelectronic Olympiad winner received the award from Rich Goldman of Synopsys. From left: Prof. Amin Bermak, Dr. Ali Iranmanesh, Mr. Rich Goldman, Mr. Reza Asadpour, Prof. Osseiran.
Mike Gianfagna, VP of Corporate Marketing
With Atrenta’s acquisition of NextOp concluded and the corporate and technology integration going forward, we checked in with Atrenta’s Mike Gianfagna about what this means for the industry. Dawn of a new business day for EDA?
Ed: It’s been about a month now since Atrenta bought NextOp. What has to happen now?
Mike: The fanfare is waning. The news has been reported and analyzed. The two company’s web sites are one. And now the real work begins as we integrate NextOp technology with Atrenta technology.
Ed: So what does all this mean?
Mike: For Atrenta, it means accelerated growth in the SoC Realization market. We can now address design and verification challenges at RTL and above. For our customers, this will mean improved schedule predictability and lower cost.
Ed: So now you add functional verification to the RTL platform for SoC design, right?
Mike: Actually, NextOp’s technology goes beyond functional verification of SoCs. It also helps with IP qualification and IP reuse – very important focus areas for Atrenta. This technology will improve the completeness and effectiveness of our IP Kit.
Customers will get the previous benefits of early analysis coupled with functional verification – an area that continues to be very time consuming, expensive and somewhat unpredictable.
Ed: So what does this mean to the EDA industry?
Mike: I hope it has a positive impact on the industry as well. EDA has been stagnant for too long. The same customers buying the same tools from the same vendors. It’s time to shake things up a bit. It’s time for new methodologies, new approaches, new business models and more positive exits for all those hard-working people at private EDA companies. Can Atrenta’s acquisition of NextOp contribute to this trend in some meaningful way? I certainly hope so.
NOTE: Lee PR does work for Atrenta.
If you missed the presentation at DAC on Digital Analog Design by Mark Horowitz, chairman of Stanford University’s Electrical Engineering Department, or want to see it again, you’re in luck. A video of his thought-provoking talk to an enthralled audience has been posted on the CEDA website and can be viewed at:
Professor Horowitz’s presentation, part of the CEDA Distinguished Speaker Series, offers a look at how analog tools can be more like digital design tools and illustrates ways to formally validate analog models, define analog fault models, and explore the effect of process variations.
To learn more about CEDA and its Distinguished Speaker, visit www.c-eda.org.
Dear Faithful Reader: Please take a few minutes to catch up on some useful news.
You have not seen this document before. It contains a summary of some topics you have seen, but there is new news throughout. Please continue reading!!
It’s a first for the EDA Commentary! Posting Part II of a fresh article, as a Blog no less, before posting Part I! But after the lengthy and often arduous process during the last three months of evaluation and choosing Altium as the fifth member of our latest EDA G5, we also wanted to be among the first, if not the first, to bring you the good news about Altium’s final quarter of its Fiscal Year, the April 1 through June 30, 2012 quarter, which quarter is the one reported as Nominal Q2 2012 for several of the EDA G5.
Nominal Q2 for the EDA G5 is normally reported in September’s EDA Commentary, and so it will be this year, when we post Part I for the other four members of the EDA G5. (We’ll include Altium’s numerical results in the collective graphs and tables in September as well).
Moreover, as a special treat, we may even include a separate, extra-bonus vignette on EDA G5 member Altium in the August 2012 EDA Commentary, the latter of which will otherwise be devoted to the EDA IP G5 Q2 financials (ARM Holdings, CEVA , MIPS, MoSys, and Rambus).
Main Message of this Blog:
It was only SIX days ago on July 19 when the following “Important Notice” was posted in the EDACafe Daily Newsletter:
Fifth EDA Vendor for future EDA Commentary Chosen!
July 19, 2012
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