January 20th, 2018
DVCon – Bigger and Better!
January 19, 2018 by Dennis Brophy, DVCon U.S. 2018 General Chair
Bigger and Better applies to DVCon U.S. 2018, but the fact is the electronic systems you design and verify grow bigger and better every year as well. It is no accident that DVCon U.S. has grown, too to keep pace with you! I am happy to share many of the details of additions we have made to DVCon U.S. to add topics of importance that are motivated by the designs you are working on today and the systems you are creating for tomorrow. We have been with you at the start of the smartphone, PC and tablet era and are with you now as new huge market potentials are on the horizon for the Internet of Things (IoT), wearable systems and intelligent embedded systems that are on a path to support fully autonomous vehicles.
From Humble Beginnings
We have seen a lot together as DVCon U.S. celebrates its 30th birthday milestone this year! The first VHDL Users Group meeting was held at the 1988 Design Automation Conference in Anaheim, CA USA during a birds-of-a-feather session. From there it has grown to be known as DVCon now being held in the United States, Europe, India and China. After that 1988 meeting, VHDL was joined by Verilog with promotion arms created for both languages. A language war was presided over and peace in a bilingual/multilingual world was embraced. From a small start, a panoply of DVCons now reach thousands of practicing design and verification engineers around the world annually. It is humbling to be part of this growth and success and even more humbling to help all design and verification engineers be that much more productive and successful.
Having been in the industry in 1988, I do recall the planning that went into the 1988 meeting, but, personally, I have no memory of attending it. If you were there in the beginning or perhaps “not yet born” or “barely out of diapers” as would be the case with younger attendees, I can assure you that this event continues to bring users together to raise awareness of design and verification challenges and share solutions from fellow engineers and tool suppliers. It is this exchange of information that brings attendees back year after year. DVCon U.S. 2018 is a highly informative and educational event we hope you will attend.
As General Chair, I am privileged to represent the work of the Steering Committee and Technical Program Committee members. They do most of the work to form the conference content with help from our conference management company, MP Associates. The following are highlights for this year.
Keynote: Christopher Tice, vice president of Verification Continuum Solutions in the Verification Group at Synopsys will deliver this year’s keynote, “Industry’s Next Challenge: The Petacycle Challenge.” This is the first time Mr. Tice will address DVCon. Mr. Tice is a longstanding and respected industry executive who has a focus to drive solutions in fast-growing verticals such as automotive, networking and IoT. Mr. Tice greatly complements this year’s program content and the future we look forward to creating.
Tutorials & Short Workshops: Of the four days of DVCon, the first and last day offer tutorials. New for this year are Short Workshops on the fourth day. The first day of tutorials is colloquially referred to as Accellera Day. This year Accellera sponsors a morning and afternoon tutorial. The morning tutorial will cover its emerging Portable Test and Stimulus standard and the afternoon will focus on the popular Universal Verification Methodology (UVM) and the work Accellera has done to complete its IEEE-1800.2™-2017 (the IEEE name for UVM) compatible reference implementation. On the fourth day of the conference, there will be six tutorials with a large focus in the afternoon on design and verification targeted at autonomous automobiles and the impact of functional safety requirements on those systems. Are there any bets on when and who will be the first person to come to DVCon in a fully autonomous vehicle?
We added the Short Workshop concept to draw more topics to provide attendees more opportunities to join in discussions and learning exercises that would not be as long and comprehensive as full tutorials. The four Short Workshops on Thursday include topics on Deep Learning for the Design & Verification Engineer, Formal Verification, Mutation Coverage for Advanced Bug Hunting and one that will seek to have the design and verification engineer focus on getting the job done without concern that underlying it all is formal technology.
Technical Papers and Posters: From novice to expert, you are covered. Design and verification practitioners are set to cover popular topics in the formal paper presentation sessions and the ever popular poster sessions. The topics covered include UVM, functional and formal verification, high-level synthesis, C/C++/SystemC, assertion based verification, Portable Stimulus, safety critical verification and ISO 26262 fault analysis, advances in low-power design and verification. The RISC-V processor core even makes an appearance with a paper on its UVM-based verification model. You will certainly find something in the program that will help in your daily design and verification activities. You get to vote on best paper and poster awards to recognize the best-of DVCon. Authors are greatly appreciative of the recognition. This year we have shared some best practices for presenters on how they can deliver better presentations. We hope this shows. If this works, we may have made your job to discern the best paper and best poster just that much more difficult.
Panel Discussions: We have two panels this year, and both will be on the third day of the conference. The first panel reflects the issue that has come with the advent of large designs: Big Data. The more and more verification information that is generated, the harder it is to find root causes to problems or system flaws. With so much information being generated, you may find it hard to attain the system coverage you seek. The panel will be a good way for industry experts to explore this more. The second panel will explore the right tool for the hardest verification jobs. This reminds me of the old adage that says “if all you have is a hammer, everything looks like a nail.” The good news for design and verification engineers is that there are many tools to choose from and the panel should help us understand which tool is best for which task. And for both panels, we will be ready and open for questions from the floor. This is your time to speak too!
Exhibits: We have just about every inch of exhibit space covered. This makes for exciting social interactions after the conference program ends, during the evening receptions or during breaks. It is a good venue for business meet-ups when the conference is in session. You will find the latest in EDA tools, design and verification IP and services represented. Armed with what you have learned in the conference setting, the exhibitors will be ready to share their advances that might help you with many of your pressing design and verification issues. Whether you are in the exhibit area or connecting with peers at the hosted lunches, you will have many opportunities to network with your peers and learn from each other.
On behalf of the DVCon U.S. 2018 Steering Committee and Technical Program Committee, I want to thank the hundreds, if not thousands of those who worked on or supported prior conferences from 1988 until today. It is their hard work and dedication that sets the stage for all of us now. I want to acknowledge the ongoing support of conference sponsors and Accellera Systems Initiative for their financial backing.
As you make your way to DVCon U.S. 2018, our conference “front door” is managed by MP Associates who has been the conference committee’s back office the past year to bring this full program to you. I want to thank them for all their work as well.
With that, I look forward to seeing many returning faces and meeting new attendees. I offer each and everyone one of you a hearty welcome to DVCon U.S. 2018! Let’s come and learn, exchange ideas and advance design and verification together.
To register for DVCon U.S. 2018 visit here. Advance registration is available through January 26th.
#DAC55 3: Last Call for Designer and IP Track presentations for 2018 event in San Francisco
January 19, 2018 by Sharon Hu - General Chair DAC55 and a professor in dept of CS and Engineering at Univ of Nortre Dame, Indiana
One of the most popular part of Design Automation Conference needs you! The Designer and IP tracks are open for submissions and you have until Jan. 23 to send in your abstracts.
These sessions are where industry experts discuss different tools, flows, and methodologies that will help you and your design team. In addition, they provide excellent opportunities for education and networking between end users and tool developers.
I’ve been to many of these sessions in recent years, and if attendance is any indication, they’ve become valuable parts of the DAC program. Mac McNamara, my predecessor as General Chair last year, compared design to putting socks on a chicken, but I can say from sitting in on several sessions that it can be done!
The Designer and IP track presentations are intended to be free of marketing and sales pitches and tuned to the needs of today’s designers. That’s a key reason they’ve become so popular. Not only will your work receive a lot of attention from fellow designers and tool users but the submission process is extremely easy.
All you need to do to is to submit a 100-word description of your presentation with six slides. Yes, you did read correctly – six slides and 100 words. If it’s accepted you can begin to educate the 2018 attendees how to put socks on those chickens!
This year’s Designer Track and IP Track will include presentations, poster sessions and a rich set of invited talks/panels for information exchange and interactions.
The DAC Designer Track brings together IC designers, embedded software and system developers, automotive electronics engineers, security experts, engineering managers, and verification engineers from across the globe. Past presenters have included AMD, ARM, Bosch, BMW, Cadence, Delphi, GM, and more.
Leading the Designer track committee is Chair Zhuo Li from Cadence. Zhuo has been a member of the DAC Executive Committee for several years and has experience in leading the Designer Track program. Zhuo is joined by designer track Vice Chairs Robert Oshana from Qualcomm/NXP and Renu Mehra from Synopsys. Rounding out the excellent team are subcommittee chairs that come from companies such as Global Foundries, AMD, Intel, NXP and Analog Devices. A complete list can be found here.
The IP track this year is chaired by Ty Garbere, here in the Silicon Valley. Ty is new to the Executive Committee but not new to IP. Ty and his team stretches from the Austin, Texas, to the Bay Area to Marseille, France (see all the names and affiliations here).
As part of our outreach to attendees for these tracks, we like to say there is no better way to improve your “Design and IP IQ” in such a short amount of time. To help improve that IQ, submit your proposed presentations today! And remember to visit the dac.com for updates as we head into the final months of planning for 2018.
Anyone who joins us for the Phil Kaufman Award ceremony and dinner knows attendees are the “who’s who” of the electronic system design ecosystem and this year’s evening will be no different. Come to “see and be seen” at The GlassHouse in San Jose, Calif., Thursday, February 8, for the Phil Kaufman Award ceremony and dinner. We will honor Dr. Rob A. Rutenbar, senior vice chancellor for Research at the University of Pittsburgh, the recipient of the 2017 Phil Kaufman Award for Distinguished Contributions to Electronic System Design.
If you attend, you’ll rub shoulders with executives from Arm, Cadence, Mentor, a Siemens Business, PDF Solutions, Synopsys and ACM SigDA who are sponsoring the evening presented by the ESD Alliance and the IEEE Council on EDA (CEDA). Attendance is open to member companies at a substantial discount. Of course, you don’t need to be a member to attend. Registration is open and information can be found at: http://bit.ly/2mt9XId
Everyone attending the dinner will help us celebrate the positive news coming from our most recent Market Statistics Service (MSS) report. As just noted in our Q3 2017 MSS report, industry revenue was up 8 percent over Q3 2016. Another positive sign –– employment in the system design ecosystem is up almost 10% when compared to Q3 2016.
The MSS newsletter can be found at: https://goo.gl/qd5bvF. Naturally, the complete quarterly MSS report has much more information, containing detailed revenue data broken out by both categories and geographic regions. The report is available to member companies of the ESD Alliance, another excellent reason to join.
About Dr. Rob Rutenbar
Rob Rutenbar’s contributions are significant and include founding multiple startups, including Neolinear, an analog tool company now part of Cadence. As an academic researcher at CMU, he pioneered a range of models, algorithms and tools for analog IC designs. During his tenure at the University of Illinois, he reworked his long-running CMU course, “VLSI CAD: Logic to Layout,” into the first Massive, Open, Online Course (MOOC) on EDA, providing training to thousands of engineers.
He’s a credit to the industry and is well deserving of the Phil Kaufman Award. Please join us in feting Dr. Rob Rutenbar. Everyone at the ESD Alliance and IEEE CEDA looks forward to seeing you February 8. Registration is open until Friday, January 26. Details are available at: http://bit.ly/2mt9XId
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NASA’s first launch didn’t reach the moon. In the quest for self-driving cars automakers are aiming for the autonomous moonshot. Competition is accelerating between major car brands, tech companies and Tesla. What advanced tech is coming to our roads and when?
Listen to the CES Panel held in Las Vegas.
Where do autonomous vehicles stand today and when will they be ready? How will they operate in connected cities and will consumers be ready to use them? Listen to this panel of experts working on autonomy share their perspectives on the current and future state of self-driving technology.
Qualcomm President Cristiano Amon is at CES to showcase the company’s latest inventions that are leading the world to 5G in industries from IoT to automotive.
Watch a replay of NVIDIA CEO Jensen Huang’s press event at CES 2018 in Las Vegas, where he unveiled new gaming technology, including Max-Q designed thin and light gaming laptops and new big format gaming displays (or BFGDs), along with a slew of auto news, including NVIDIA DRIVE Xavier processor, DRIVE IX and DRIVE AR as well as partnerships with Volkswagen, Uber, Baidu, ZF and Aurora.
RTOS memory footprint
January 15, 2018 by Colin Walls
Most of the time, I subscribe to the view that “the only stupid question is the one you did not ask”. However, I do have trouble with a question that I have been asked countless times at trade-shows, seminars etc. The question is “How much memory does Nucleus RTOS need?”
It is not that this is a stupid question. It is very sensible to be fully aware of resource utilization with deeply embedded systems. The problem is that I am rarely sure how to give a meaningful and useful answer, so I resort to generalities and this is often viewed with suspicion. The reason for this is that the answer is dependent upon a great many variables …
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