September 22nd, 2016
Geoff Tate, founding CEO at Rambus, is busy – again. These days he’s leading the charge with a new FPGA-based enterprise that, per Tate, wants to be “the first to the party” – a party that’s all about providing FGPA-based IP to a market increasingly in need of these products.
When Tate and I spoke by phone recently, he offered the Flex Logix elevator pitch, and then focused on the company’s August press release.
“We are like the ARM of FPGA,” Tate said, and then laughed. “No, we are not expecting to be acquired by SoftBank anytime soon.”
“However, ARM was the first to successfully embed processors,” he said, “and at Flex Logic we are [doing that] with FPGAs.”
PCB Tools, Part 2: Request for info
September 22, 2016 by Peggy Aycinena
Last year a blog was posted in this space talking about tools for PCB design: PCB Tools, Part 1: Zuken, Mentor, Cadence, Altium. Lengthy and detailed, that discussion included commentary on the state of the art, and the market, for PCB design tools.
Now it’s time to assemble Part 2 of the discussion, which will be posted here in early November. This second installment intends to include input from more than just the four companies in the first article.
Custom Compiler In-Design Assistants (Part 3)
September 20, 2016 by Graham Etchells, Director of Product Marketing at Synopsys
In the blog ‘Custom Compiler In-Design Assistants (Part 2)’, I outlined how we can use StarRC to report capacitances on critical nets in the layout even when the design is still in flux and not completely LVS-clean. In addition to capacitance reports, we also showed resistance reporting which is critical for FinFET-based layouts. At advanced nodes, the impact of parasitics, electromigration (EM) and restricted design rules drive critical layout choices. Interconnect that does not meet resistance, or EM criteria and unbalanced capacitances on matched nets, can and often does adversely impact layout schedules. So the earlier in the layout phase the layout engineer can address these issues, the sooner he or she can close the design.
EM in particular is a notorious problem in the FinFET process due to the high drive of the transistors and thin metals. So let’s say, for example, the layout engineer has to route a critical net which could be susceptible to the impact of EM. This is a non-trivial task that could be quite challenging. However, if you use Custom Compiler, there are some very cool capabilities that make laying out interconnect that meets EM criteria very quick and very easy.
In its third year, DVCon India 2016 was held in Bangalore September 15-16, hosted in the Leela Palace, as it was in 2015, an island of serenity, peace and comfort in the center of Bangalore.
Although I don’t want to repeat myself, my 2015 report included my assessment that “the traffic on Bangalore’s roads reminded me of a Circle of Hell from Dante Alighieri’s 14th-century poem, ‘Divine Comedy.’” It was like that again this year. As if this wasn’t enough, the timing of this year’s conference coincided with an unanticipated and unpleasant event.
A little background. Bangalore is the city center of the Karnataka State bordering the Tamil Nadu State. The border is delimited by the river Cauvery that provides crucial and life sustaining water to the two states via a dam. In good years, the dam has enough water to fulfill the needs of both. In bad years, the scarcity of water causes grief, tensions and confrontations. The Summer of 2016 was really bad. I was told that the discord between the two states turned into an enormous political crisis that escalated to the attention of the Prime Minister of India.
Device registers in C
September 19, 2016 by Colin Walls
Mentor Graphics has historically been dedicated to providing tools for electronic hardware designers and that still represents a very large proportion of the business. Ever since I was acquired into the company, I have found that the hardware focused guys have a healthy interest in software – embedded software in particular. Often, they are specifically concerned with the boundary between software and hardware …
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