EDACafe Weekly Review December 12th, 2017

WIT and Wisdom with Women in the Workplace …
December 11, 2017  by Julie Rogers

A large and enthusiastic crowd greeted five high-powered women panelists as they took the stage two weeks ago to talk about “Empowering Leadership with WIT and WISDOM” with Ann Steffora Mutschler of Semiconductor Engineering. The memorable evening was co-hosted by ANSYS, the ESD Alliance and SEMI at SEMI’s new headquarters in Milpitas, Calif.

Ajit Manocha, SEMI’s president and CEO, offered a welcome and conveyed the organization’s commitment to advancement in the workplace as attendees began settling in. He suggested that a better title for the evening would be “WIT and WISDOM with Women in the Workplace,” that got plenty of smiles and heads nodding in agreement.

At the WIT and Wisdom panel (standing from left to right): Amita Dharwan, Annapoorna Krishnaswamy, Renuka Vankuri, Neela Kulkarni, Panelist Indira Joshi, Vic Kulkarni, Moderator Ann Steffora Mutschler, Panelist Sundari Mitra, Julie Rogers and Panelist Mona Sabet. Kneeling from left to right: Dhrithi Bankuru, Emine Bostanci and Jason Woo.

I’m sure audience members, a mix of men and women, will take heed to the pearls of wisdom from the empowering 90 minute-long discussion. Ann asked each panelist to focus on an area, from personal branding and leadership to negotiation, networking and mentoring. She captured valuable insights each of the women made in a great wrap-up article that includes photos of the evening. It can be found at: http://bit.ly/2Apad0C. A recording of the panel is posted on the ESD Alliance website, along with additional photos, at: http://bit.ly/2jc5ffQ.

Partition your Design for FPGA Prototyping
December 11, 2017  by Henry Chan

Modern ASIC and SoC designs have increased in complexity such that multiple FPGAs of the largest capacity are now required to prototype the entire functionality of the design. As design sizes increase, more and more FPGAs are required. The capacity and pin limitations of FPGAs create constraints for how the ASIC/SoC design can be mapped into the FPGAs. Aldec’s HES-DVM’s prototyping mode accounts for the limitations of the target FPGAs and allows the user to map a design to the FPGAs within these constraints.

Partitioning a design to fit into multiple FPGAs can be a lot of work

Designing the partitions with HES-DVM is as easy as selecting specific VHDL/SystemVerilog design modules from the hierarchy and moving them to a desired partition. All information about the design modules and the amount of LUTs, Flip-flops, memory blocks, DSP slices, and I/O consumed are displayed for convenience. These values can also be viewed as a percentage of the target FPGAs’ available resources allowing you to know when an FPGA is full.

Adding a module to a partition

Mapping a partition to an FPGA

Once the partitions are finalized, each partition can be assigned to a specific FPGA. A design successfully fitting into the FPGAs on the target prototyping board is only the beginning. There still remains a big problem with the sheer number of connections between the partitions. Modern designs have thousands of internal signals interconnecting major blocks or sub-systems. It’s likely that there won’t be a sufficient amount of direct connections between FPGAs to support the design’s internal wiring. How can the large amount of internal design signals possibly be accommodated by the relatively smaller amount of I/O available from the FPGAs?

For the rest of this article, visit the Aldec Design and Verification Blog.

REUSE 2017: Opportunity knocks, Who’s answering
December 7, 2017  by Peggy Aycinena

 


This week on Thursday, December 14th
, the second annual edition of REUSE 2017 will unfold in Silicon Valley. It’s a gathering crafted specifically for the vendors of IP blocks, and now whole sub-systems, those pieces of the puzzle which allow the vendors’ customers to design and produce electronic products more efficiently and with better results.

It goes without saying that IP is a pivotal part of the semiconductor supply chain today. Organizations like Arm and Synopsys reap huge benefits from being among the principal suppliers of that IP. But there are hundreds of IP companies in the world – big, medium, and small – that also provide IP.

Potentially, they could all be participating in something like Reuse 2017. Arm, for instance, is participating in the conference, along with dozens of smaller companies. Synopsys, however, is not.

 


Academics are a special breed of animal
, especially those who have also succeeded in business. They vacillate wildly between the conventional and the visionary, between the tangible realities of life and the far-flung concepts of blue-sky, what-if thinking. And this year’s Kaufman Award winner is no exception.

Professor Rob Rutenbar grew up in the suburbs of Detroit, did his undergrad at Wayne State University, his PhD at University of Michigan, was on the faculty at Carnegie-Mellon for 25 years, during which time he co-founded Neolinear and sold it to Cadence, and then picked up and moved to the University of Illinois Urbana-Champaign, where he put the university and his own perseverance to the test by igniting the move to massively available online education. Now just this year, he has returned to the East Coast as Senior Vice Chancellor for Research at the University of Pittsburgh.

All of this is very comprehensible and logical, but only on the face of things.

In fact, by his own admission, no small part of Rutenbar’s success is based on attendance at a random barbecue years ago, a bit of simultaneous happenstance, and a restless interest in what’s around the next corner. Which of course, is the classic definition of a bohemian. Or in Rutenbar’s case, the definition of a Kaufman Award winner.

[Spoiler alert: The following may include narrative that will appear in Rob Rutenbar’s talk on Thursday, February 8, 2018, when he accepts the Kaufman Award at the CEDA/ESD Alliance dinner in his honor in San Jose.]

DownStream: Solutions for Post Processing PCB Designs


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