EDACafe Weekly Review February 23rd, 2017

ESD Alliance Bulletin: DVCon, New Member Helic, Upcoming Events
February 23, 2017  by Bob Smith, Executive Director

I promised in my last post a special blog post with great photos highlighting the Phil Kaufman Award Ceremony and Dinner January 26. It will go up Monday.

But first, the news that the ESD Alliance will exhibit at DVCon at the DoubleTree Hotel in San Jose, Calif. We’ll be in Booth #100 in the foyer, so please stop by if you’re attending.

During DVCon, we’re co-hosting with OneSpin Solutions a panel, “Ride with the Verify Seven,” moderated by Jim Hogan of Vista Ventures featuring six verification leaders who grew their companies from startup to medium-sized industry player. It will be held Monday beginning at 7 p.m., after the Booth Crawl, until 8:30 p.m. Light refreshments and drinks will be served.

Panelists include:

  • Andy Stein, Vice President of North American Sales from Avery Design Systems
  • Adnan Hamid, CEO at Breker Verification Systems
  • Phil Moorby, Chief Architect of Montana, a Phil Kaufman Award recipient presented to him by the ESD Alliance and IEEE CEDA for inventing the Verilog language
  • Raik Brinkmann, President and CEO of OneSpin, an ESD Alliance Member Company
  • Prakash Narain, President and CEO at Real Intent, an ESD Alliance Member Company
  • Rick Carlson, ESD Alliance Member Company Verific’s Vice President of Sales and advisor to seven early-stage startups

The event is open free of charge to all Alliance member companies and DVCon attendees. Non-members of the Alliance or anyone without a DVCon badge are invited to attend for a fee of $40. Registration information and more details on the event can be found at: http://bit.ly/2kNWx6T

Helic Joins the Alliance

Helic, a leading supplier of EDA software for crosstalk analysis and signoff of high-frequency analog/RF and high-speed SoC design, is a new member of the Alliance. Helic joined for a variety of reasons, including networking activities such as the Phil Kaufman Award dinner, and emphasized the industry initiatives, such as Export, License Management and Interoperability, as important initiatives. It intends to be an active participant in all. Also noteworthy is the Market Statistics Service (MSS), a tool that will support Helic’s forecasting efforts.

Mark Your Calendars for Upcoming Alliance Events

More details will be forthcoming about “Energy Policy and Strategy for the IoT Era,” Thursday, March 23. A panel of experts will discuss how the California Energy Commission’s new rules and standards affect the semiconductor design ecosystem, including EDA, IP, embedded software and other technology vendors that supply products to PC system manufacturers.

Two weeks later, we’ll host the “CEO Outlook,” Thursday, April 6. It will feature members of the ESD Alliance Board: Simon Segars, CEO of ARM, Lip-Bu Tan, Cadence’s President and CEO, Wally Rhines, Chairman and CEO at Mentor, and Aart de Geus, Chairman and CEO of Synopsys. We’ll have more information soon.

Now is a good time to join the ESD Alliance! I’m available to answer any questions about the Alliance and why your company show join. Please contact me at bob@esd-alliance.org, or check out our website at: www.esd-alliance.org

Come Ride with the Verify Seven, the Next-Gen Verification Leaders
February 17, 2017  by Bob Smith, Executive Director

I’m now able to share with EDACafe readers the news about an exciting evening panel we’re co-hosting with OneSpinSolutions titled, “Ride with the Verify Seven,” during DVCon Monday, February 27.

It will be moderated by industry luminary Jim Hogan of Vista Ventures and features six well-known and readily recognizable verification leaders who grew their companies from startup to medium-sized industry player:

  • Andy Stein, Vice President of North American Sales from Avery Design Systems
  • Adnan Hamid, Chief Executive Officer (CEO) at Breker Verification Systems
  • Phil Moorby, Chief Architect of Montana, a Phil Kaufman Award recipient presented to him by the ESD Alliance and IEEE CEDA for inventing the Verilog language
  • Raik Brinkmann, President CEO of OneSpin
  • Prakash Narain, Real Intent’s President and CEO
  • Rick Carlson, Verific’s Vice President of Sales and advisor to seven early-stage startups

#54 DAC 4: DAC’s Designer and IP Tracks and the limits of social media
February 17, 2017  by Michael (Mac) McNamara, Gen Chair 54th DAC; Pres & CEO Adapt-IP

When it comes keeping the growth of design productivity exponential, a key barrier that fell in the past ten years is due to the increasing use of social media, which set free the exchange of focused, expert knowledge, from user to user.  On the web we have very helpful company-curated user forums; and often even better, the stack-exchanges which are user curated, where readers up-vote the most helpful content and as a result these are often the very best place to visit to get unstuck from a problem you recognize you have.

These forums and posts are all reactions against the underfunded, or poorly directed tech publishing team, tasked perhaps by marketing (or the simple desire to keep their employment) to only document what works; and never mention an alternative solution.

Of course a web search will also take you to the swampy places where all you find is others who are stuck with similar problems, and they just bemoan that the vendor doesn’t care, or take you through a litany of things they’ve tried that didn’t work.  One also finds the beginning of tutorials, part one of what was to be a twenty volume tutorial where the blogger planned to impart the wisdom of the ages for how to build the magical thing – and only part one got written – and even that is now out of date.

So, search works great — when you have an idea what the problem is, and you are following a large crowd who has been there before, and they’ve taken the time to create hints.

 

Going hands-on at last year’s Designer/IP track session, with no marketeers in sight!

DownStream: Solutions for Post Processing PCB Designs
TrueCircuits: IOTPLL


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