EDACafe Weekly Review March 21st, 2018

Greetings from Dresden, Germany! I’m attending DATE (Design, Automation & Test in Europe), a lively conference sponsored by the ESD Alliance covering a range of topics related to electronic system design.

A reminder that Thursday, April 5, is the date of the 2018 ESD Alliance-hosted CEO Outlook, a rare chance to hear from C-level executives and an opportunity to compare notes on trends and networking with other attendees. Attendees will be able to talk with panelists to learn their thoughts on the semiconductor design ecosystem before they head to the stage. Panelists are Arm’s Simon Segars, Dean Drako of IC Manage, Wally Rhines from Mentor, a Siemens Business, and Sonics’ Grant Pierce. Ed Sperling, editor-in-chief of Semiconductor Engineering, will serve as moderator. Each of the four panelists will present a brief opening statement about the future of the industry that will lead to a discussion about trends and opportunities. An interactive and moderated audience discussion will follow.

Simon Segars

Dean Drako

Wally Rhines

Grant Pierce

Ed Sperling

The event will be held at Cadence Design Systems’ Building 10 in San Jose, Calif., Thursday, April 5. We set aside time during the evening for attendees to interact with senior executives, especially member companies who are invited to a private reception from 5:30 p.m. until 6:15 p.m. An open reception including food and drinks will begin at 6:15 p.m. The panel will start at 7 p.m.

We hope you can join us. The evening is open free of charge to all ESD Alliance member companies. Non-members can attend for a fee of $40. Registration information can be found at: http://bit.ly/2p9NNwj Seating is limited.

Our CEO Outlook isn’t the only event we have planned for April. Later in the month, we will host a morning-long workshop on digital marketing. Watch this space for more information.

If your company is not a member of the ESD Alliance, we invite you and your company to join. Visit the ESD Alliance website to read about our varied events program, technical committees and other initiatives. Please contact me with your questions about why joining the ESD Alliance is important for staying current about the semiconductor design ecosystem. I can explain ROI or other justifications for joining the ESD Alliance. I can be reached at bob@esd-alliance.org

Engage with the ESD Alliance at:

Website: www.esd-alliance.org

ESD Alliance Bridging the Frontier blog: http://bit.ly/2oJUVzl

Twitter: @ESDAlliance

LinkedIn: https://www.linkedin.com/groups/8424092

Facebook: https://www.facebook.com/ESDAlliance



SystemVerilog Functional Coverage in a Nutshell
March 15, 2018  by Henry Chan

Let’s say you have a block you need to verify. How do you know that the stimulus you are about to use is exhaustive enough and that you have covered the necessary scenarios/situations to prove it is working correctly? This is where functional coverage comes in. SystemVerilog’s functional coverage constructs allow you to quantify the completeness of your stimulus by recording the values that have occurred on your signals.

Consider an 8-bit address signal, paddr, and a 32-bit data signal, pwdata. Assigning a coverpoint to each signal will direct your simulator to track these signals during simulation and record the number of hits. For each coverpoint, bins can be created to organize the possible signal values into meaningful categories. Finally, a covergroup is used to encapsulate it all and is instantiated using the new() constructor. Associating the covergroup with a clock event is also a good way to trigger the coverage sampling.

Industry Struggles with System Coverage
March 15, 2018  by Adnan Hamid, CEO of Breker

DVCon is a great place to talk to design and verification engineers. As the Accellera Portable Stimulus Standard (PSS) gets closer to reality, we were able to share with them during the conference the progress made and the ways in which it may impact their task. Most of them are as excited about PSS as we are. While we have been working in this field for more than a decade and have received a lot of feedback, there are now many more people becoming aware of it and the potential that it has. This provides us with the opportunity to learn as well.

Blinking is good
March 15, 2018  by Colin Walls

I like simple things. In particular, I like clean and simple ways to solve a problem. For example, user interaction with an embedded system might be something very slick – touch screen LCDs seem to be fitted to everything nowadays. But sometimes a simple LED indicator is enough. It is amazing how useful a simple blinking light can be …

DownStream: Solutions for Post Processing PCB Designs

You are registered as: [jraja@lat36.com].

CafeNews is a service for EDA professionals. EDACafe.com respects your online time and Internet privacy. Edit or Change my newsletter's profile details. Unsubscribe me from this newsletter.

Copyright © 2018, Internet Business Systems, Inc. — 25 North 14th Steet, Suite 710 San Jose, CA 95112 — +1 (408) 882-6554 — All rights reserved.