January 17th, 2017
January 16, 2017 by Colin Walls
I have often talked about the process that might be applied to the selection of an embedded operating system and I hope that I can provide some guidance. However, developers tend to stick with a specific OS [or, at least, with a particular OS vendor] – recent research suggested that only about 20% of developers anticipated a change of OS for their next project.
I started thinking about why there is this apparently high degree of loyalty …
As we embrace a New Year, it is always a toss-up as to whether we are drawn to look to the past to understand our future, or to the future itself. The blank page. The untested waters. The mysterious frontier. Danger and opportunity seemingly mixed in equal proportions within the murky fog a-swirl in that not-so-crystal ball.
It’s within that spirit that I recalled this week a reverie that unfolded several years back while sailing the waters of Lake Gatun midst the Panama Canal. A reverie that attempted to synchronize the muscular optimism at the turn into the last century with the somewhat more tenuous outlook at the turn into this one.
That earlier reverie was tempered by remembering innovations such as the Vienna Secession, Futurism, Fin de siècle, Dada and Cubism – movements that propelled some observers from the nineteenth century into the twentieth – could hardly be said to reflect a stridently cheery outlook. Inversely, the angst and anxiety that oft-times characterize the narcissism of our own here-and-now – trends that have sometimes accompanied our complex journey from the twentieth century into the twenty-first – are profoundly repudiated by the engineering marvels that define this equally muscular New Age.
In truth, the past was never as rosy as we remember and rarely does the future fulfill our darkest premonitions. It’s simply the nature of the human comedy that we so thoroughly believe they do.
Are you building the IoT? Then you already know it’s a jungle out there.
Happily, the University of New Hampshire is offering an interesting service that should help. They’ll test your IoT device to see if it meets current Internet Protocal standards. Of course, understanding such a service presumes there are any standards in the first place – there are many, some very controversial – and also presumes you know how those standards are described within a veritable jungle of acronym-laden jargon.
But before we run through that rain forest of gobbledygook, let’s first review what the goals of the UNH InterOperability Lab are in establishing their IoT IP Testing Service. Those goals were laid out during an online press conference in December when the folks at the lab explained what they want to accomplish: Foster industry-wide collaboration, provide an extensive testbed for evaluating IoT devices, and train the engineers of tomorrow who want to help build the IoT.
These are clearly commendable goals, and the people behind the effort seem nothing if not cheerful and upbeat, but to fully understand what they’re doing you’ll first need to slog through the acronyms. Buckle your seat belt, it’s going to be a bumpy ride.
Trouble Ahead, Trouble Behind
January 12, 2017 by Graham Etchells, Director of Product Marketing at Synopsys
Happy New Year!
There’s no doubt that FinFET technologies have been very appealing. With FinFETs being up to 37% faster while using less than half the dynamic power than planar transistors, they have been a ‘no brainer’ to adopt and the industry has embraced them. To that extent, in a recent survey of Synopsys users, more than a third of those who responded plan to use FinFET technologies on their next chip.
Since its introduction, the technology has been rapidly evolving. Take TSMC, for example.
TSMC’s 16FF+ (FinFET Plus) technology features FinFET transistors with a third-generation High-k/Metal Gate process, a fifth generation of transistor strain process, and advanced 193nm lithography.
As a result, this latest 16nm technology offers substantial power reduction for the same chip performance. Now foundries are pushing even lower into 10nm and even 7nm process geometries.
In previous blog posts I outlined some of the many challenges that the first generation of FinFET technologies introduced into the custom layout flow. Many of you will be hitting these issues for the first time as 16nm and 14nm technologies move into the mainstream. For those moving beyond the 16/14nm generation, there is trouble ahead as a whole new set of issues must be overcome.
For nodes below 16/14nm we see new challenges related to design rules, layout effort, variation and analog/digital co-design. So over the next few weeks I will unfold the gory details of these emerging challenges.
Here’s hoping 2017 is a productive year for us all as we meet our challenges head-on!
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