EDACafe Weekly Review October 20th, 2017

For a long time I have been a fan of code coverage tools that are embedded into the simulators themselves, and which give you the ability to switch easily between the code and the coverage results. It is particularly helpful to have a way of navigating the hierarchy, selecting a coverage result and then being able to look into the source code and make changes.

I recently had occasion to explain to someone how the feature works in Aldec’s Riviera-PRO, and to reflect on the tool developments that led to this great capability. As you may be aware, Aldec has a number of legacy coverage tools that allow you to view the coverage results from within the simulator; and which give you easy access to the coverage results and the corresponding lines of code. With the introduction of our unified coverage database – in .acdb format – it became possible to see the code coverage results in a more flexible format. The biggest boost, in my opinion, was the introduction of a cross-probing capability.

For those of you who are wondering how to use this feature.

  • Open Riviera-PRO 2016.06 or newer and run your design with Coverage Enabled.
  • Open the datasets window (View-> Hierarchy and Objects-> Datasets).
  • Right-click in the window and select Add.
  • Add the .acdb file associated with your design (it should show up as Simulation n, where n is number).
  • Click on the newly added database.

For the rest of this article, visit the Aldec Design and Verification Blog.

Zynq-based Embedded Development Kit for University Programs
October 17, 2017  by Farhad Fallahlalehzari

Creativity and innovation, which lead the society to success, rest on the foundational institutions such as schools and universities. They provide fertile soil to seed, grow and flourish enterprises. To harvest more within an industry, the ecosystem needs to be enriched where the seeds are grown. Considering that the university’s courses are the nutrition to student, they need to be designed in a productive manner as they will provide the next generation of engineers. By providing the necessary platform in addition to the rich and informative tutorials, the quality of the input information for students would be assured. Particularly in the field of Electrical and Computer Engineering, it is important that students get as much hands on experience as possible, and tackle design challenges – such as HW/SW co-design and co-verification – before entering the job market; for their own benefit as well as the industry as a whole.

In this blog, you will become familiar with the TySOM Education kit (TySOM EDU) package designed for the university courses related to hardware design and embedded system design researches.

The TySOM EDU contains a TySOM embedded development board, Riviera-PRO advanced hardware simulator and informative tutorials and reference designs. Although it is possible to choose any development board from the TySOM embedded development board family, the TySOM-1A-7Z010 would be the most cost-effective solution for most university projects.

TySOM-1A-7Z010 (ZynqTM) is a ready-to-use and feature-rich embedded development board which provides the required peripherals to tackle both basic and advanced Zynq-based projects. The XC7Z010 is based on the Xilinx® All Programmable System-on-Chip (SoC) architecture, which integrates a dual-core ARM Cortex-A9 processor with Xilinx 7-series Field Programmable Gate Array (FPGA) logic. Coupling the device to a rich set of peripherals for connectivity, communication and multimedia, makes this board ideal for university projects requiring HW/SW co-design.  For the rest of this article, visit the Aldec Design and Verification Blog.

In an open-source world, it’s all about integration
October 16, 2017  by Colin Walls

I have historically been somewhat skeptical about open source software (OSS). I am always wary of anything that is “free” and subscribe to the TANSTAAFL (“there ain’t no such thing as a free lunch”) principle. It has taken me quite a few years to understand that open software is not free – it is just a different business model from the usual “we make it, you buy it” approach.

I am only now coming to grips with how the OSS model really works, why it is a good thing and how business can leverage it to mutual benefit …

Verific: SystemVerilog & VHDL Parsers


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