EDACafe Weekly Review September 26th, 2016

The Tate Effect: Confidence in Flex Logix Team & Technology
September 22, 2016  by Peggy Aycinena

 


Geoff Tate, founding CEO at Rambus, is busy – again.
 These days he’s leading the charge with a new FPGA-based enterprise that, per Tate, wants to be “the first to the party” – a party that’s all about providing FGPA-based IP to a market increasingly in need of these products.

When Tate and I spoke by phone recently, he offered the Flex Logix elevator pitch, and then focused on the company’s August press release.

“We are like the ARM of FPGA,” Tate said, and then laughed. “No, we are not expecting to be acquired by SoftBank anytime soon.”

“However, ARM was the first to successfully embed processors,” he said, “and at Flex Logic we are [doing that] with FPGAs.”

PCB Tools, Part 2: Request for info
September 22, 2016  by Peggy Aycinena


Last year a blog was posted in this space talking about tools for PCB design
: PCB Tools, Part 1: Zuken, Mentor, Cadence, Altium. Lengthy and detailed, that discussion included commentary on the state of the art, and the market, for PCB design tools.

Now it’s time to assemble Part 2 of the discussion, which will be posted here in early November. This second installment intends to include input from more than just the four companies in the first article.

Custom Compiler In-Design Assistants (Part 3)
September 20, 2016  by Graham Etchells, Director of Product Marketing at Synopsys

In the blog ‘Custom Compiler In-Design Assistants (Part 2)’, I outlined how we can use StarRC to report capacitances on critical nets in the layout even when the design is still in flux and not completely LVS-clean. In addition to capacitance reports, we also showed resistance reporting which is critical for FinFET-based layouts. At advanced nodes, the impact of parasitics, electromigration (EM) and restricted design rules drive critical layout choices. Interconnect that does not meet resistance, or EM criteria and unbalanced capacitances on matched nets, can and often does adversely impact layout schedules. So the earlier in the layout phase the layout engineer can address these issues, the sooner he or she can close the design.

EM in particular is a notorious problem in the FinFET process due to the high drive of the transistors and thin metals. So let’s say, for example, the layout engineer has to route a critical net which could be susceptible to the impact of EM. This is a non-trivial task that could be quite challenging. However, if you use Custom Compiler, there are some very cool capabilities that make laying out interconnect that meets EM criteria very quick and very easy.

CST Webinar Series
S2C: FPGA Base prototyping- Download white paper
TrueCircuits: IOTPLL


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