EDACafe Weekly Review December 10th, 2016

Registration Opens for Phil Kaufman Award Dinner, More News from the ESD Alliance
December 9, 2016  by Bob Smith, Executive Director

Registration opened this week for the Phil Kaufman Award Presentation and Dinner to honor Andrzej Strojwas, chief technologist at PDF Solutions and Keithley professor of Electrical and Computer Engineering at Carnegie Mellon University. AndrzejTrophyGraphic

I hope you’ll join us for a celebration that helps us kicks off 2017. The dinner will be held Thursday, January 26, at the Fourth Street Summit Center in San Jose, Calif., where we held the dinner paying tribute to Mentor Graphics’ Wally Rhines in 2015. The evening will begin with a reception and cocktails at 6:30 p.m. The dinner and award presentation will be run from 7:30 p.m. until 9 p.m. We have special entertainment planned that will challenge your senses!

Andrzej is being recognized with the award, presented annually by the ESD Alliance and the IEEE Council on Electronic Design Automation (CEDA), for his pioneering research in the area of design for manufacturing (DFM) in the semiconductor industry.

Reservations are $175 per person for ESD Alliance and IEEE members or $250 per person for non-members. Seating is limited and we can accept R.S.V.P.s until Thursday, January 12. To reserve your seat at the 2016 Phil Kaufman Award Presentation and Dinner, visit our online registration.

Tables of 10 are available if your company be interested in sponsoring the event. Sponsorships will heighten a company’s visibility and brand exposure through positive publicity and promotion, and through signage and the program at the event. By sponsoring the dinner, your company is showing the community that it believes in the vibrancy of our industry and honoring those individuals who created it.

To find out more, visit our sponsorship page or call (408) 287-3322.

Constrain Me, Please
December 8, 2016  by Adnan Hamid, CEO of Breker

In the movies, when a person acts irrationally they are usually declared to be mad and quickly placed in a straitjacket for the protection of themselves and those around them. If we continue those thoughts into the world of verification, SystemVerilog must be declared to be a mad language.

CST Webinar Series
TrueCircuits: IOTPLL


You are registered as: [jaehyun.kim@skhynix.com].

CafeNews is a service for EDA professionals. EDACafe.com respects your online time and Internet privacy. Edit or Change my newsletter's profile details. Unsubscribe me from this newsletter.

Copyright © 2016, Internet Business Systems, Inc. — 595 Millich Dr., Suite 216 Campbell, CA 95008 — +1 (408)-337-6870 — All rights reserved.