EDACafe Weekly Review December 5th, 2016

Reducing Analog Cell Layout Time with the Symbolic Editor
December 1, 2016  by Graham Etchells, Director of Product Marketing at Synopsys

Hello again!

In the last blog post I profiled the use of Custom Compiler’s Symbolic Editor for rapid digital cell layout.

In this post, we will tackle analog cell layout and show some more of the Symbolic Editor features that enable analog layout engineers to complete their layout in minutes vs. hours.

As with the digital cell layout, engineers can take advantage of the Symbolic Editor’s ability to define multiple P and N row pairs, as shown in Figure 1.


Figure 1. Multiple Row Pairs

The preview window shows how the layout will look when realized on the layout canvas. In this example, it is clear that in order to make the design more compact, the larger transistors need to be folded.

Folding the transistors is very easy using the Symbolic Editor. Options on the toolbar allow the designer to fold the transistor by specifying either the number of segments desired or by specifying a width threshold. Once the option is set, all the layout engineer has to do is simply select the appropriate devices and have them folded such that the transistors fit neatly in the rows. Figure 2 shows how the design looks before and after folding.



Figure 2. Before and After Folding

Analog designs are very sensitive to process variation, noise and other manufacturing variances. In order to mitigate the impact of these variances on critical pieces of circuitry, layout engineers use complex interdigitation patterns in addition to other layout techniques. This is a critical practice for analog design, because the effects of the variances, if not accounted for, can lead to a non-functioning piece of circuitry.

The Symbolic Editor provides a simple way to implement these complex patterns via the Pattern Generator. As well as being able to specify your own patterns, the Pattern Generator also includes a library of built-in patterns that can be used to interdigitate devices in a specific order. Take a differential pair, for example. The layout engineer can choose from a variety of different patterns as shown in Figure 3.



Figure 3. Pattern Generator

The preview window makes it easy to see how the layout will look with the chosen pattern and, once the engineer is happy with the choice, s/he simply realizes the layout on the canvas. Figure 4 shows the results of choosing a Common Centroid pattern. With no constraints to enter, no code to write, layout is done in minutes vs. hours.



Figure 4. Highlighted Devices as Part of a Common Centroid Pattern

Transistors are not the only devices that can take advantage of the Symbolic Editor. In the automotive world, it is often necessary to lay out banks of resistors. This is something the Symbolic Editor can also help with. Resistors can be chained serially in a variety of different routing patterns.

Using the Symbolic Editor allows the layout engineer to make simple graphical choices of how the layout needs to look and then have the detailed placement taken care of by the placement engine. It makes it easy to add or remove placement rows and columns, as well as insert dummy devices. Figure 6 shows the completed symbolic layout of two resistor banks with automatic insertion of dummies.


Figure 6. Completed Symbolic Layout of Two Resistor Banks with Automatic Insertion of Dummies

Generating devices and placing them such that they meet all the design rules and produce a robust working design is about 30% of the time spent doing layout. Using a layout assistant like the Symbolic Editor really speeds this task up and makes the layout engineer much more productive. Synopsys has invested heavily in this technology over a period of 5+ years, such that we can address a broad range of design applications, unlike the recent offerings from other EDA vendors. Applicable to both FinFET and established planar CMOS nodes, the Symbolic Editor makes analog cell layout quick and easy.

To learn more about how the Symbolic Editor can help to rapidly create analog cells, check out Custom Compiler Webisode #6 that shows the Symbolic Editor in action.

Continuing a tradition started in the early days of the company, the European edition of the Mentor Graphics’ User Group meeting, now renamed User2User or U2U, was held Tuesday, October 11, in Munich, Germany.u2u

In the opening remarks Matthias Knoppik, Mentor Graphics’ Area Director Northern-Central Europe, expressed his excitement for the record attendance, and briefly presented the agenda for the one-day event. Two keynote presentations and seven technical tracks packed the day, from 9:15 a.m. to 4:30 p.m. An exhibit area setup with podiums mounted by computers gave Mentor’s partners the opportunity to demonstrate their products.

The first keynote was delivered by Malcom Penn, Chairman and CEO of Future Horizon, a market research and analysis enterprise. Titled “Caveat Emptor: The Triumph of Hype vs Reality,” Malcom highlighted the four factors that influence industry growth: the economy, unit growth, capacity or the ability to make those units, and the price exacted from them. In discussing each of them, he peppered the delivery with anecdotal and ironic references with lighthearted spirit. It was an enjoyable presentation.

The second keynote was presented by Dr. Walden (Wally) C. Rhines, Chairman and CEO of Mentor Graphics. Titled “Predicting the Next Wave of Semiconductor Growth,” it perfectly matched Malcom’s earlier keynote, prompting Wally to draw few parallels between the two. As is always the case, Wally did a terrific job. In this instance, what impressed me was Wally’s use of the Gompertz curve to predict the sectors with the best potential growth in the semiconductor industry. As Wally explained, the curve or function, was conceived in 1825 by Benjamin Gompertz, a British self-educated mathematician. It is a mathematical model for time series and is used widely to predict things that happen in time, like the growth of tumors, population growth, bubble foam uptake, market impacts and finance, and so on. It has withstood the test of time.

Wally applied the Gompertz curve to several test cases to show what the future could look like. He started with desktop PCs, today growing at negative rate. He moved on to notebooks, again with a negative growth-rate, but with a probability to ship 40% of the total notebooks ever built in the future. He continued with cell phones, smart phones, internet use, IoT, set-top boxes, smart meters, fitness trackers, medical wearables, electric vehicles, data centers, gateways and data storage. Wally also discussed transistor production, and predicted its future using the Gompertz function.

For more on Wally’s keynote and how the Gompertz curve can be applied to the semiconductor industry, see my latest blog post on EE Times.

For the technical tracks, I attended SoC Functional Verification, which complements my area of expertise. The track opened with a keynote by John Lenyo, Vice President and General Manager of the Design Verification Technology Division of Mentor Graphics. John presented industry trends in today’s verification landscape, starting with the growth in verification productivity based on growth of transistors per design engineer, drop in EDA cost per transistor, and decrease in total IC revenues per transistors. This was followed by charts on the rising verification complexity with emphasis on design security and safety critical design, comparing the worldwide trend to the European trend. A set of slides focused on design verification best practices, with a chart that mapped the past and anticipated future growth in emulation adoption.

Five technical presentations filled the SoC Functional Verification tack.

Nigel Elliot from Mentor and Thomas Alofs from STMicroelectronics delivered an interesting test case on the verification challenges and solutions in designing a mixed-signal USB Type-C device.

Daniel Gruber from Univa presented a detailed analysis of the benefits of Univa Grid Engine to manage the workload of a modern multi-user, multi-job, emulation platform in a datacenter. I will write about this technology and its benefits in a future piece.

Pranab Saharia of ARM, U.K., presented a paper titled “Reckoning GPU Power with Veloce.” Pranab first highlighted the limits of using simulation on estimating power dissipation in today’s complex SoC designs. He then described the adoption of the Veloce emulation platform to estimate the power consumption of the ARM Mali GPUs, the generation of the SAIF files for average power consumption, and the creation of the Switching Activity Graph plotting the peak power. A set of benchmark data concluded his presentation.

Antti Rautakoura from Nokia in Finland presented a step-by-step verification management methodology with emphasis on functional coverage.

Dr. Carol Marsh from Leonardo, one of the biggest suppliers of defense equipment to the U.K. Ministry of Defence (MoD), presented a test case on adopting UVM with a large development team. Given the nature of the Leonardo business, no slide handouts were allowed. From memory, I recall that the team was able to switch from designing entirely in VHDL without any knowledge of Verilog to adopting SystemVerilog and UVM across the board in 18 months or so. This is an absolute record that gives credit to management for supporting the trial, but also to the training put in place. Mentor’s Verification Academy was highly prized for helping to achieve this ambitious goal. It goes without saying that the engineers were motivated and included the cream of the crop in the category.

All told, it was an exceptional event starting with the two keynotes. The presentations I saw in the SoC Functional Verification Track were first rate. Kudos to the organizers of U2U for making the event memorable.

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