EDACafe Weekly Review October 6th, 2012

The EDA & MCAD/MCAE Almanac – Nominal Q2 2012
October 6, 2012  by Dr. Russ Henke

Dear faithful blog reader: Please take a few minutes of your valuable time to read the October 8, 2012 article, “The EDA & MCAD/MCAE Almanac – Nominal Q2 2012”

You may reach the new October 8 Commentary via two different paths:

(1)      Returning to the front page of EDACafe.com, and scrolling down the front page, finding a box with a URL posted with a photo of yours truly, and clicking on the title in the box:


(2)      By clicking here right now on the URL below to go directly to the article:



Optimize your Mixed Signal Verification Environment – Part 1
October 5, 2012  by Hélène Thibiéroz

With increasing complexity of mixed-signal designs comes a more and more expensive coverage scheme for verification, from the analog as well as the digital side. Finding a verification cockpit combining ease-of-use, performance and required features for both Analog and Digital is therefore not a trivial task.

If you think about it, you need an environment able to support both Analog and Digital domains, all potential configurations as well as various language extensions (SPICE, Verilog, VHDL, VerilogA, VerilogAMS,….). You also need to cover a large design space, requiring an efficient way to run multi tests in parallel, to display both analog and digital results simultaneously and troubleshoot any accuracy/convergence issues.

With that in mind, I wanted to further develop on Synopsys CustomerExplorer Ultra and how this platform fits today verification needs. But rather than just giving you a list of features or a datasheet, I wanted to focus on key points of CXU using small videos. I know, I am a nice person 🙂

I have therefore asked several CXU experts to demo some of those features. In this 4 minute video, Manu Pillai is showing us the spice debugging features of CustomExplorer Ultra’ s Connection View:

Multi-net connectivity/Full schematic display: CXU’s Connection View is highly interactive. It accepts the designs in the netlist format and allows the user to display the signal path relevant for the debugging. It is capable of showing the connectivity of multiple nets and complete schematic, so that user can visualize their netlist .

Waveform Cross Probing: User can link the existing or newly created waveform file with the Connection View and cross probe the signals. This is very useful for the debugging purpose.

Parameter report and W/L report: Netlists may have lot of parameters with expressions and CXU will evaluate these expressions and gives the parameter report. The W/L report gives the width & length information of all the MOS devices in the design. These reports will be useful to identify unreasonable parameter definitions or width and length values.

Enjoy the movie 🙂





M&A: Synopsys acquires EVE
October 4, 2012  by Peggy Aycinena


Synopsys announced today it has completed the acquisition of EVE, the French emulation company that provides platforms for SoC verification. The terms of the acquisition were not disclosed.

I interviewed Lauro Rizatti, General Manager and Marketing VP for EVE-US, in May of this year. [You can read that interview here.] Given the vigor of the messaging out of EVE at the time, it has come as a surprise to many, but undoubtedly not all, that EVE was acquired this week.

Per today’s Press Release issued by the two companies: “Emulation is a rapidly growing solution in the spectrum of technologies used to verify today’s highly complex SoCs. Integrating EVE’s technology with Synopsys’ best-in-class platform of simulation, debug, verification IP, coverage, static verification, low power verification, FPGA prototyping and virtual prototyping solutions will give Synopsys customers access to the broadest verification offering in the industry.

Elsip: Data Management Engine IP
October 4, 2012  by Peggy Aycinena


Swedish startup Elsip launched its first product on October 2nd, the Data Management Engine [DME], which the company says “is a programmable and configurable synthesizable IP block that solves cache coherency, memory consistency, virtual address translation and dynamic memory allocation for distributed, private or shared memories in heterogeneous and homogeneous architectures.”

I spoke with Elsip CEO Adam Edstrom at the Sophia Antipolis Microelectronics Forum in France on October 3rd. He told me Elsip is based on research out of the Royal Institute of Technology in Stockholm, in particular the work of professors Axel Jantsch, Ahmed Hemani, and Zhonghai Lu. The company was incorporated last year, but the patent-pending product has been many years in the making.

Per Edstrom: “The world is going to multicore, but many areas like robotics, embedded systems, and military systems are not using multicore because the demands of shared memory cannot be met. With DME, however, we are providing a scalable solution to the problems that occur when there are lots of cores on a chip, and lots of memory. The user assigns one DME per core and because the DME is programmable with application specific micro-code, when there are multiple kernels trying to access the same memory, problems do not arise.”

Ashima Dabare

Saurabh Verma








On the heels of EE Times editor Brian Bailey naming their article “Understanding clock domain issues” the number one article on EDA Designline, we checked in with authors Saurabh Verma and Ashima Dabare on what they see as developments and new challenges since they wrote their 2007 article. Here’s what they said.

Ed: It appears that your article got twice the number of views as the number two article. Congratulations on the EE Times recognition!

Obviously, CDC was an important design issue in 2007 and it certainly is today. What would you say to designers today?

Ashima: CDC design is evolving and so are the synchronization techniques and verification tools. Since we have written this article we have witnessed new challenges posed to CDC verification tools.

One that comes to mind is evolving synchronization styles. In addition to clever variations of synchronization techniques introduced by designers trying to meet their design objective or schedule, new architectures such as those required for a network on a chip (NoC) have been introduced which in turn require verification tools to re-invent themselves.

Recently CDC tools have introduced generic synchronization verification techniques that do not rely on the structure of the synchronizer and analyze clock domain crossings at the protocol level allowing them to better recognize synchronizers, reduce “noise” and improve root cause analysis.

Saurabh: Also, global chip design dictates blocks and IPs to be designed in various geographical locations. The person doing CDC verification is rarely the designer. CDC verification tools are now challenged with providing root-cause analysis of CDC problems to people who have little knowledge of the block.

I also see as a fact that design size is fast growing and so are the number of clocks and clock domains. Combined with the move toward global chip development, flat CDC verification of large SoCs would be a painful exercise where bugs can easily slip through.

The divide and conquer approach seems to be the best possible approach. To begin with, the lower level blocks should be analyzed and CDC issues, if any, should be fixed at the block level itself. Once all the individual blocks are CDC clean, their abstract models can be plugged in and the complete design can be analyzed for CDC issues at the interconnect level.

Ed: So how would you sum up what CDC design needs in 2012?

Ashima: With the ever increasing complexity of design styles, robust CDC verification is indispensable to enable successful chips in the first silicon attempt!


Note:  as near as we can tell, Atrenta is the only company to place two articles in Bailey’s top ten. Narayana Koduri’s Power awareness in RTL design analysis came in as ninth most read. We’ll catch up with him next week, so stay tuned.



Note: Lee PR does work for Atrenta

M&A: Rumor dampens spirits over cocktails
October 2, 2012  by Peggy Aycinena


It’s not often that the rumor hits the fan that Synopsys is buying EVE, it’s not often that you’re standing in a cocktail party at a tech conference in the South of France, and it’s not often that these two events happen simultaneously.

When the Synopsys/EVE rumor swept through the cocktail party in Sophia Antipolis on this first evening of the SAME Forum, not surprisingly a lot of people had opinions. This is not just a tech conference, after all, it’s a microelectronics conference with an emphasis on design; EDA is at the center of the conversation.

This is also Europe and at the moment EVE, headquartered in France, is the darling of the EDA ecosystem on the Continent. The company is doing very well, is felt to be holding its own in a series of lawsuits with Mentor Graphics, and is widely admired overall. Needless to say, the reaction over cocktails that EVE may go the way of SpringSoft and Magma was not one of jubilation. Just the opposite, in fact.

Attend CST Webinar

You are registered as: [_EMAIL_].

CafeNews is a service for EDA professionals. EDACafe.com respects your online time and Internet privacy. Edit or Change my newsletter's profile details. Unsubscribe me from this newsletter.

Copyright © 2018, Internet Business Systems, Inc. — 25 North 14th Steet, Suite 710 San Jose, CA 95112 — +1 (408) 882-6554 — All rights reserved.