August 29th, 2013
Tezzaron Founder and CTO Bob Patti delivered a rousing keynote at the Silicon Valley Magma User Group meeting back in 2010, talking about his company’s 3D memory technology and how it offered a solution to the increased demands for on-chip capacity. I spoke to Patti following that speech, with details of the conversation posted here.
In the past 3 years, things have only gotten worse with respect to memory demands, so one might think Tezzaron’s solution is in even greater demand today. The problem, of course, is that Tezzaron Semiconductor is not the only company offering something that looks like ‘3D memory.’
In fact, 3 weeks ago at MemCon 2013 in Silicon Valley, I attended a keynote given by Micron Technology’s Mike Black singing the praises of his company’s Hybrid Memory Cube. Sitting in the audience, I tried to compare and contrast the Micron technology with what I believed to be the Tezzaron solution.
Happily, Tezzaron had a booth at MemCon, so it was possible to talk to somebody from the company about how they viewed Micron’s competing technology. Unfortunately, Tezzaron VP David Chapman was surrounded by a mob of interested people when I got to the booth, so I took his card and arranged to talk to him later about my many questions.
My number one question: Given the size of Micron and the ecosystem of partners they’ve assembled, the Hybrid Memory Cube Consortium, is Tezzaron winning the battle of technology superiority, but losing the war for market share?
Tezzaron’s Chapman was not offended by my question. Instead, he started by framing his answer with a description of current market needs and continued from there. The following is a transcript of his comments.
Andrew B. Kahng, Professor of CSE and ECE, Univ. of California at San Diego presented a paper on “The ITRS Design Technology and System Drivers Roadmap: Process and Status” at the 50th Design Automation Conference in Austin, TX. This important review of the technology challenges that are in front of the EDA industry and what is the current status is presented here below in this fifth part of a blog series.
5. LOW-POWER DESIGN
In response to power and energy being identiﬁed as the grand challenge for the semiconductor roadmap, the Design TWG in 2011 added a Low-Power Design technology roadmap to the Design Chapter. The low-power design roadmap contains a mix of future solutions spanning electrical, functional and software realms . Projected low-power design innovations include (i) frequency islands and near-threshold computing at the circuit level; (ii) heterogeneous parallel processing, many core software development tools, and hardware/software co-partitioning at the architecture level; and (iii) power-aware software and software virtual prototyping at the software level. Figure 8 shows that with low-power innovations the SOC-CP driver dissipates 3.5W (with 48.8M logic gates) in 2011. Low-power design innovations will help limit the power to 8.22W when the number of logic gates grows by more than 40x to 1995.5M in 2026.
Perfectly suited by nature to teaching, when affable Cliff Cummings steps up to conduct his Verilog course, the class is in for a treat. From the get-go, Cliff establishes a tone of respect, humor, and openness to questions of any kind. He encourages students to interrupt when they don’t understand, to stand up, sit down, resort to coffee and/or carbs, and in all ways to relax and enjoy the learning experience.
There’s something additional, however, that Cliff brings to his inspired task of teaching and that’s his decades of involvement with the Verilog language, its evolution, standards, and implementation. What Cliff Cummings doesn’t know about Verilog and SystemVerilog, isn’t worth knowing. Period.
This week, Cliff is teaching Verilog-2001 Design & Best Coding Practices in Silicon Valley – specifically, in the offices of EDA Direct – and I’ve been lucky enough to attend. Not being a Verilog expert, I approached the class with some trepidation, but found to my delight that I was not the only one among the 8 engineers in the room “new” to the language. We’re all engineers, but we’re not all Verilog designers and hence it’s a class perfectly suited to our skills, interests, and goals.
As the proud Product Manager of Aldec’s FPGA Design Simulation solution, I am excited (like it was my first Cranberries concert) to announce that Active-HDL™ is celebrating 16 years since its initial release in 1997. Active-HDL has not merely stood the test of time, it has dominated the FPGA market like a Hulk Hogan smackdown with powerful simulation performance and debugging tools.
The key to Active-HDL’s long-term success lies in Aldec’s customer-centric philosophy. Simply put, we really do listen closely to our users and invest heavily in our tools. For this reason, continued simulation performance optimizations from release to release enable users to benefit from Active-HDL’s faster simulation even as the size of FPGA designs continues to grow.
Atrenta will discuss what RTL signoff requirements are needed for SoC designers in China, South Korea and Taiwan at their upcoming seminars in September and October.
Click here for more information.
LPR does work for Atrenta
From the blog stats it seems clear that late August is a slow time with lots of folks on vacation, so I’ll take a break from the heavy technical topics to chat about the industry. Long before I worked for an EDA company, I was an active participant as a user of EDA tools and as a CAD manager tasked with evaluating them and integrating them together. In that role, I loved working with interesting startups that had new ideas for electronic development.
It was part of my job to follow the EDA industry closely so that we could choose our tool investments based on both strength of technology and likelihood of vendor success. It seemed to me that the industry was divided into only three categories: major leaguers, minor leaguers, and startups. I observed that nearly all EDA startups disappeared after three or four years, with three possible endgames: acquisition, initial public offering (IPO), or bankruptcy.
You are registered as: [_EMAIL_].
CafeNews is a service for EDA professionals. EDACafe.com respects your online time and Internet privacy. Edit or Change my newsletter's profile details. Unsubscribe me from this newsletter.
Copyright © 2016, Internet Business Systems, Inc. — 595 Millich Dr., Suite 216 Campbell, CA 95008 — +1 (408)-337-6870 — All rights reserved.