August 25th, 2014
The EDA editorial brain trust today is the topic of our continuing conversation with Richard Goering and Brian Fuller.
ED: What is the EDA editorial brain trust these days?
RICHARD: Not sure how you’re defining “brain trust,” but if there is one, it’s with the vendors and the independent on-line publications.
ED: Who makes up the EDA editorial brain trust?
RICHARD: If you add it all up, there are still a number of editors with deep EDA and semiconductor experience – they’re just no longer with print publications.
Additionally, there are now a number of writers and bloggers who didn’t start as journalists but who turned in that direction during the transition away from print.
Thirty two hours ago, the earth let loose here in Northern California delivering up a 6.0 earthquake 5 miles southwest of Napa in the heart of the wine country. It was the biggest earthquake we’ve experienced in the region since the 1989 Loma Prieta quake, which was a 6.9 on the Richter scale.
The thing about earthquakes is that they come on you suddenly, which is scarier than hell. Nonetheless, at a Sunday afternoon party yesterday in Silicon Valley, where the earthquake was felt even though the epicenter was 80 miles away, a Bay Area native said, “We may not know an earthquake’s coming, but I’d still rather live here than in places where they’ve got tornadoes. Now those are really scary!”
Ironically, on local radio this morning a geologist based in the Midwest was being interviewed about yesterday’s South Napa quake and concluded by saying, “You know, we may have tornadoes in our area, and they are pretty darn scary, but I’d far rather live here than where you guys are. At least we have warning when a tornado’s bearing down on us!”
But is that implication true? Is there no such thing as a warning prior to an earthquake? Well, for those of us who live in Earthquake Country, we are beginning to think [hope] differently.
Mixed-signal silicon design, bringing the worlds of analog and digital technology onto a single die, has never been an easy task. Formerly, the analog and digital teams would work independently on their designs, leaving the place and route team with the thankless task of integrating everything onto a single chip. A microcontroller design, with all of its carefully thought out peripherals, would be routed leaving analog-sized holes for the oscillator, ADC and transceivers needed to complete the design.
Several posts back, we introduced the idea of “composing” higher-level verification elements from low-level elements with little or no effort. We discussed how this was not possible with traditional testbench elements such as virtual sequencers and scoreboards. We showed that Breker’s graph-based scenario models can be simply combined from the block level to the cluster level, and from the cluster level to the full-chip level.
Last week, we took the unusual step of announcing a new EDA product via social media rather than a traditional press release. The news about TrekUVM clearly spread; we had a nice spike in blog readership and an even bigger spike in traffic to our Web site. Since our readers have interest in this new product, we’d like to continue talking about it and, specifically, show how it fosters model composition and vertical reuse.
During a recent trip to Austin, Texas, I spent some time with Aldec Partner, Victor Lyuboslavsky of Victor EDA and creator of the EDA Playground. Victor EDA is one of those organizations that Aldec aligns easily with because we share a strong commitment to accelerate learning within the engineering community by providing the right tools, training and resources.
As a result of this partnership, we are pleased to announce that Aldec Riviera-PRO EDU™ Advanced Verification Platform is now available on EDA Playground.
Here’s an excerpt from Victor’s recent guest blog post on the Aldec Design and Verification Blog, that illustrates how engineers can benefit from leveraging this tool to practice UVM & SystemVerilog simulation:
You may have found yourself among those eyeing the job market and wondering, “How hard is it to switch fields and become a verification engineer?”
You are registered as: [_EMAIL_].
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