January 21st, 2016
CDC Verification of Fast-to-Slow Clocks – Part 2: Formal Checks
January 21, 2016 by Dr. Roger B. Hughes, Director of Strategic Accounts
We continue the short blog series that addresses the issue of doing clock domain crossing analysis where the clocks differ in frequency. In Part 1, we ended the discussion noting that when there is a fast-to-slow transition, there is a possibility that a short duration control pulse may be completely missed by the receive domain and a formal analysis is required to discover if this is a potential problem. We will look at how formal analysis can verify this kind of transition.
A formal check also is required on a slow-to-fast data crossing with feedback. In such a circuit, as shown in Figure 4, an acknowledge signal coming from the receiving fast-clock domain to the transmitting slow-clock domain also requires a formal Pulse Width check. Although the control pulse (request) is going from slow to fast and does not need a formal pulse width check, the acknowledge pulse-width check is necessary because the acknowledge signal (the feedback circuit) is going from a fast to a slow clock and, in order for the acknowledge to be properly captured, the acknowledge pulse (transmitted from the receiving side) must be sufficiently wide to be captured (received on the transmitting side) by the slower clock domain of the transmitting side flops. Failure to check for this condition is the reason behind many a request/acknowledge circuit not working as expected. Note that feedback circuits in a fast-to-slow crossing are operating in a slow-to-fast mode and the acknowledge signal in such a circuit does not need to be pulse-width checked. In short, all fast-to-slow control signal transitions, whether connected in a feed-forward or a feedback manner need to be formally pulse-width checked to ensure integrity of the control aspect of the clock domain crossing.
Just short of 2 years ago, the EDA press corps sat in a room in the Hyatt Regency in Santa Clara and enjoyed a face-to-face with Cadence CEO Lip-Bu Tan. A full report of that conversation is available here, but it is the closing segment of the report that informs this blog:
Finally, the Cadence PR machine closed out the hour by making sure the Press Corps was privy to the human side of CEO Tan. It would appear his wife does not make the tech-product purchasing decisions at home as much as do the two boys. Tan said that his two CMU-educated engineer sons are smart and savvy, and had advised him early on to invest in both Netflix and Tesla. Tan humbly acknowledged that he had, unfortunately, ignored those two pieces of advice and hence had lost out on the opportunity to win big in both movies and EVs.
So, here’s the hypothetical: Given Lip-Bu Tan’s involvement with a $2 billion investment group – efforts interleaved with his responsibilities as Cadence CEO – wouldn’t it have been wise to harvest stock tips from his press meeting back in March 2014 in Santa Clara?
Semiconductor IP Revenue Surges into Double Digits
January 20, 2016 by Bob Smith, Executive Director
Let’s tip our glass of champagne to 2016, which started off on a high note for the EDA industry. The EDA Consortium’s Market Statistics Service (MSS) reported revenue for Q3 2015 increased 7.1 percent to $1957.5 million compared to $1828.1 million in Q3 2014.
Coverage of our news was positive on our industry onlines and elsewhere, though there was an interesting “first” in the numbers that deserves highlighting. In Q3 2015, the Semiconductor IP (SIP) segment showed the highest revenue out of all categories tracked by the MSS at $653 million. For the first time, SIP exceeded Computer Aided Engineering (CAE) at $635 million.
What a difference 20 years makes! Back in Q3 1996, SIP was the smallest revenue category being tracked and showed $15 million in revenue. Taken over the past 20 years, the SIP segment has grown, on average, at 20% per year –– a seemingly remarkable achievement. Or is it?
The IP revolution has been underway for quite some time and has had a profound impact on electronics design. Chips now are a collection of small and large blocks of IP stitched together along with value-added circuitry created by the chip design team. It is not uncommon to find that IP blocks make up 60-70% or even more of the real estate on these large chip designs.
As someone who has lived in the heart of Silicon Valley for more than 30 years, I’m used to the regular cries that we’re losing our innovative edge. Every few years something happens to cast some doubt on our future: a stock market crash, a major company moving elsewhere, or a lot of press about some new Silicon Forest/Glen/Mountain/Prairie/Island/Whatever trying to beat us at our own game.
Sure, we face plenty of challenges. A recent article on SemiWiki painted a rather cautionary view of today’s Silicon Valley. But there’s good news too. Silicon “Valley” has grown to include San Francisco and much of the Bay area, with corresponding growth in technology employment and impact. Today, I’d like to springboard from a recent post on semiconductor mergers and acquisitions to consider one particular aspect of the current role of Silicon Valley.
Industry onlines have been posting 2016 predictions since the beginning of the year, so why should EDACafe be any different?
Herein is my 2016 prediction: The Electronics Industry will see more hardware emulation experts and specialists this year than ever before due in large measure to the widespread proliferation of hardware emulators. These experts are both hardware designers and software developers –– giving hardware emulation the distinction of being the only verification tool able to make this claim –– as co-verification becomes a way of life for SoC debug. They become proficient emulation users as the tool tracks a bug across software and into the hardware design and the reverse, from the hardware design to the embedded software.
Another reason why we’ll see more experts can be attributed to hardware emulators now being used as datacenter resources, making them more accessible to more users. These efficient tools can be accessed remotely in transaction-based emulation mode or in standalone emulation mode any time anywhere.
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