July 2nd, 2015
Once again it’s an acquisition, and once again the lucky winner’s Synopsys. This time the prize is Elliptic Technologies, “a provider of cryptography cores, security protocol accelerators and processors, Root of Trust embedded security IP modules, secure boot and cryptography middleware, and content protection IP for integration into SoCs. [In other words], security IP cores and software solutions for mobile, automotive, digital home, IoT and cloud computing applications.”
Per the Press Release: “Elliptic’s integrated solutions enable the most efficient silicon design and highest level of security to help prevent a wide range of evolving threats in connected devices such as theft, tampering, side channels attacks, malware and data breaches. As a founding member of the prpl Foundation’s Security Working Group, Elliptic has been dedicated to defining an open security framework for deploying secured and authenticated virtualized services in the IoT and related emerging markets.”
I was an organizer for the industry DAC panel on “Scalable Verification: Evolution or Revolution?” held during the second week of June in San Francisco. While the industry generally agrees on methodologies used to verify IP blocks or subsystems, we lack consensus on approaches required to verify SoC integration and system-level functionality of embedded systems. One of questions addressed by the panelists was “Can existing standards and methodologies be extended to address system-level challenges, or are new approaches required?”
The panel was moderated by that veteran verification technologist Brian Bailey. He was excellent in steering the panelists through this deep topic. The panelists were all from semiconductor companies (not EDA) and included the following:
- Ali Habibi, design verification methodology lead at Qualcomm
- Steven Jorgensen, architect for the Hewlett-Packard Networking Provision ASIC Group;
- Bill Greene, CPU verification manager for ARM
- Mark Glasser, verification architect at Nvidia.
Brian has written an excellent article on the panelists insights in his column on SemiEngineering.com. Here are a few quick snippets to entice you in reading the entire piece:
“Simulators are not making effective use of the advances in the underlying hardware. Design sizes are growing faster than the improvements they are making.”
“Design reuse has not helped us, and even if you change only 20% of a design you still have to completely re-verify it. We need to be able to describe features and functionality in an abstract manner, and from that derive the inputs to the verification tools.”
“You might think that we are able to re-use much of our verification collateral from the IP, unit and top levels into the system-level environment, but this isn’t the case. You can’t find new bugs by running stimulus that was used in the past, and this means that the notions of coverage are different.”
You can read the entire column at this link: Wrong Verification Revolution Offered. Be sure to add your comments at the end and let Brian know what you think is missing in verification.
If you’re interested in Wearables and the IoT, you need go no further than talking with Mentor Graphics, in particular the company’s spokesman Warren Kurisu. Warren and I spoke by phone last month, our conversation sparked by two aggressively confident press releases out of Wilsonville.
* Mentor Graphics announces its Embedded Nucleus RTOS framework includes a complete range of features targeting next-generation wearable IoT devices for the medical, fitness, and security markets.
* The new release of Mentor’s Nucleus RTOS targets connected embedded devices for high-performance, advanced IoT applications, utilizing process model technology that enables developers to reconfigure, update, and provision connected embedded devices that utilize cloud-based remote software services.
The IoT being at the center of all of this, I asked Warren to define the IoT. He said, “That’s an interesting challenge, because it actually depends on the industry.
Richard Goering at his 30th DAC, San Francisco in 2014
Richard Goering, the EDA industry’s distinguished reporter and most recently Cadence blogger is finally closing his notebook and retiring from the world of EDA writing after 30 years. I can’t think of anyone that is more universally regarded and respected in our industry, even though all he did was report and analyze industry news and developments.
Richard left Cadence Design Systems at the end of June (last month). According to his last blog posting EDA Retrospective: 30+ Years of Highlights and Lowlights, and What Comes Next he will be pursuing a variety of interests other than EDA. He will “keep watching to see what happens next in this small but vital industry”.
When Richard left EETimes in 2007, there was universal hand-wringing and distress that we had lost a key part of our industry. John Cooley did a Wiretap post on his DeepChip web-site with contributions from 20 different executives, analysts and other media heavyweights. Here are a just few quotes that I picked out for this post:
What’s so Special about Your SoC Design Data?
June 30, 2015 by Tom Anderson, VP of Marketing
Last week on The Breker Trekker, we discussed the resurgence of interest in EDA tools in the cloud. Like our first post on the topic two year’s ago, last week’s entry was very popular. Clearly this is a topic of interest to both our regular and occasional readers. Two more announcements regarding EDA in the cloud also surfaced during the recent Design Automation Conference (DAC), so it does seem as if there is more effort going toward finding a technically and financially successful industry solution.
Last week we summarized five barriers that have helped prevent cloud-based EDA from achieving mainstream adoption:
- The EDA vendor’s effort to port to a cloud-based platform
- Worries about GUI and interactive responsiveness
- Ability to support users of cloud-based tools
- Lack of an established, proven business model
- Concerns over security of the design and verification data in the cloud
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