April 18th, 2015
Thanks to the widespread reuse of intellectual property (IP) blocks and the difficulty of distributing a system-wide clock across an entire device, today’s system-on-chip (SoC) designs use a large number of clock domains that run asynchronously to each other. A design involving hundreds of millions of transistors can easily incorporate 50 or more clock domains and hundreds of thousands of signals that cross between them.
Although the use of smaller individual clock domains helps improve verification of subsystems apart from the context of the full SoC, the checks required to ensure that the full SoC meets its timing constraints have become increasingly time consuming.
Signals involved in clock domain crossing (CDC), for example where a flip-flip driven by one clock signal feeds data to a flop driven by a different clock signal raise the potential issue of metastability and data loss. Tools based on static verification technology exist to perform CDC checks and recommend the inclusion of more robust synchronizers or other changes to remove the risk of metastability and data loss.
Building on last year’s success, the 2015 Design Automation Conference in San Francisco is offering even more substantial content in the track centered on silicon IP and design reuse. Reading through the list of topics, speakers, and companies set to be featured across a diverse set of sessions from June 7-9 at Moscone Center, two things are obvious.
One, a lot of work has been done to assemble all of this. And two, it’s possible the thorny issues surrounding IP reuse may never go away: integration, verifying quality, convincing staff to use design blocks that originate outside of the group, and dealing with the massive amounts of data that IP selection and reuse generates.
The Ever-Changing EDA Landscape
April 16, 2015 by Tom Anderson, VP of Marketing
In last week’s post on The Breker Trekker blog, we surveyed the semiconductor market for the past 15 years or so from the standpoint of revenue leadership. Wikipedia provides a set of tables showing the top 20 semiconductor vendors for each year. We compiled this data into a single table, and found that this revealed some clear trends of how the industry has evolved during this period. The many spin-offs, mergers, acquisitions, and bankruptcies resulted in constant changes in the lower ranks of the top 20, and even some shuffling among the top players. This topic proved to be of great interest to our readers, with this week-old post surpassing many popular older posts.
Last week we also contrasted the semiconductor market with the EDA market, in which the top three revenue leaders have been the same for more than 20 years. Unlike semiconductors, there are almost no other EDA companies beyond the top three that were around 15-20 years ago and still exist today. We have had many spin-offs, mergers, acquisitions, and bankruptcies in our industry as well. Like semiconductors, we have had many changes in rankings beyond the very top tier, so we thought that we would try this week to create a similar chart and perform a similar analysis for EDA. However, this has not proven possible. We’d like to explain why and offer some more thoughts on the EDA market and how it differs from semiconductors.
Power consumption is an issue. With portable devices this affects battery life. [I am irritated by the short intervals between necessary charging sessions with my smartphone, for example.] With mains powered equipment, power consumption is also a concern for environmental reasons. The matter of power has always been seen as a “hardware issue”, but, of late, there has been an increasing interest in the role of software …
Quarterly, as many of you know, the Market Statistics Service of the EDA Consortium reports out on the health of the industry. Quarterly, as well, Mentor CEO Dr. Walden Rhines makes himself available to the Press, to comment and elaborate on the EDAC results.
And so it was last Friday that I had a chance, yet again, to speak by phone with Rhines, always a conversation to look forward to. If you want to know how the EDA industry did in Q4_2014, you can scroll to the bottom of this blog. If you want to read a paraphrased snapshot of a wide-ranging discussion with Wally Rhines, however, it follows here.
WWJD – This debriefing thing must be quite tedious. How’s it going, and how’s EDA doing?
Rhines – This is only my second Press meeting, so not bad. The EDA industry [booked] record revenues for the fourth quarter of 2014, and the entire year, and showed a substantially higher rate of return than the semiconductor industry. The industry’s doing very well, with hiring up 6 percent on the year, and strong reporting from companies in IP and physical design and verification. There is some weakness in the numbers out of Japan, but they were offset by strong results in the PacRim and the Americas.
DVCON was, well, DVCON…nothing out of the ordinary; it was as always well-attended with good traffic, perhaps even more than I have seen previously. The one good thing I noticed, and this is technically very important: the food and drink is getting better and more plentiful each year.
Anyway, for the most part, my sources had similar comments; they picked up some nice leads and met some of the customers they were trying to meet. In reality, that is all a trade show can hope to accomplish for its vendors.
Similar to DAC, I don’t write about the seminars etc.–my meetings are done on the exhibitor floor. Two good things did happen for me: I did another video, which you can see on EDACafé with the other DVCON interviews at http://www10.edacafe.com/video/Video-Categories-2015-DVCon-Video-Interviews/10418/category.html, and I finally met Peggy, who like Oprah needs no last name mentioned. I was impressed as she was quite lovely.
I finally read enough articles about high level synthesis (HLS) that give a sense of hype that just didn’t seem to be matched by what I’ve heard. Now hype is pretty subjective, but numbers are not. For example, the High Level Synthesis group on LinkedIn only has 66 members (including myself!); compare that to the FPGA – Field Programmable Gate Array group which has 22,931 members (also including myself). If we were to suppose that HLS tools target FPGA users – which most tools (such as Vivado HLS, NEC CyberWorkbench, ImpulseC, etc.) do, and assuming that both FPGA users and HLS users have a LinkedIn account, then we might conclude from these numbers that less than 0.3% of FPGA users are interested in HLS.
System coherency remains an important factor for SoC design starts. The ARM® CoreLink™ CCI-400 has seen great success, over 35 licensees across multiple applications from mobile big.LITTLE, to network infrastructure, digital TV and automotive infotainment. In all these applications there is a need for full coherency for multiple processor clusters, and IO coherency for accelerators and interfaces such as networking and PCIe.
Compared to CoreLink CCI-400, the recently-announced CoreLink CCI-500 offers up to double the peak system bandwidth, a 30 percent processor memory performance increase, reduced system power, and high scalability and configurability to suit the needs of diverse applications. This blog will go into more detail on these benefits, but first I’ll give a quick recap of cache coherency and shared data.
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