EDACafe Weekly Review December 17th, 2017

#55DAC 2: Teams tackle deep learning in DAC design contest
December 13, 2017  by Sharon Hu - General Chair DAC55 and a professor in dept of CS and Engineering at Univ of Nortre Dame, Indiana

 

When it comes to tackling leading-edge design challenges in fun ways, there’s no better place than DAC. For DAC 2018, we’ve created a System Design Contest targeting machine learning on embedded hardware.

If you think this is too leading edge for a design contest, you’d be mistaken: More than 100 teams registered for the contest. You can find a full list of the teams here: http://www.cse.cuhk.edu.hk/~byu/2018-DAC-HDC/teams.html

So how does the contest work:

Teams had the choice of using a Xilinx PynQ-Z1 FPGA-based development system or an NVIDIA Jetson TX2 development system, as well as software and deep-learning tools kits. Xilinx and NVIDIA donated boards to support the efforts.

Drone maker DJI donated a data-set that included more than 100 video clips with full annotation of the bounding box for the tracking object (a person or car).

The teams built either FPGA- or GPU-based systems to track people and vehicles from consumer drones using deep learning methods running on advanced embedded systems platforms. A hidden dataset is used to evaluate the performance of the designs in terms of accuracy and power consumption.

I can’t over-state the energy and generosity of the contest sponsors—NVIDIA, Xilinx, DJI, ACM/SIGDA and DAC— in this endeavor.  Thank you! It’s so rewarding to see industry and innovators come together to enable superb system design.

It’s been an honor to work with industry luminary Chris Rowen, and the University organizers Yiyu Shi at Notre Dame, Jingtong Hu at University of Pittsburgh and Bei Yu at the Chinese University of Hong Kong on this project.

The teams will be posting results at the end of each month, starting in late January, so you can follow their progress leading up to DAC.  Mark your calendars and follow the teams as they design to win cash awards sponsored by Nvidia and Xilinx.  Awards will be given to the top three teams in each category, and the top winners will be on hand in San Francisco at DAC to present their work.

 

 

Recently, we had the opportunity to interview Grant Imahara at the Arm TechCon 2017 Conference in Santa Clara, CA.

Grant is the celebrity engineer spokesperson for Mouser Electronics, the leading global New Product Introduction (NPI) distributor. Grant is an electrical engineer, roboticist, and television host. He is best known for his work on the television series MythBusters, where he designed and built numerous robots and specialized in operating the various computers and electronics that were utilized to objectively test myths. More recently, Grant has partnered with Mouser Electronics in launching its Empowering Innovation Together program, where he hosts webisodes and contributes blog posts and articles.

Grant visited our EDACafe exhibition booth at Arm TechCon for an interesting interview that covered many topics, including his relationship with Mouser Electronics.

Interview with Grant Imahara at Arm TechCon 2017

 

EDACafe: Can you discuss your relationship with Mouser Electronics and what you do with the company?

Grant I: I am Mouser’s celebrity engineer spokesman, which is kind of funny because generally speaking, engineers are not the rock stars and don’t often get the recognition we deserve for all the amazing things that we do. Mouser said, “Let’s take a person who is a known face from TV, who is also an engineer and make them our spokesperson.” So, here I am.

WIT and Wisdom with Women in the Workplace …
December 11, 2017  by Julie Rogers

A large and enthusiastic crowd greeted five high-powered women panelists as they took the stage two weeks ago to talk about “Empowering Leadership with WIT and WISDOM” with Ann Steffora Mutschler of Semiconductor Engineering. The memorable evening was co-hosted by ANSYS, the ESD Alliance and SEMI at SEMI’s new headquarters in Milpitas, Calif.

Ajit Manocha, SEMI’s president and CEO, offered a welcome and conveyed the organization’s commitment to advancement in the workplace as attendees began settling in. He suggested that a better title for the evening would be “WIT and WISDOM with Women in the Workplace,” that got plenty of smiles and heads nodding in agreement.

At the WIT and Wisdom panel (standing from left to right): Amita Dharwan, Annapoorna Krishnaswamy, Renuka Vankuri, Neela Kulkarni, Panelist Indira Joshi, Vic Kulkarni, Moderator Ann Steffora Mutschler, Panelist Sundari Mitra, Julie Rogers and Panelist Mona Sabet. Kneeling from left to right: Dhrithi Bankuru, Emine Bostanci and Jason Woo.

I’m sure audience members, a mix of men and women, will take heed to the pearls of wisdom from the empowering 90 minute-long discussion. Ann asked each panelist to focus on an area, from personal branding and leadership to negotiation, networking and mentoring. She captured valuable insights each of the women made in a great wrap-up article that includes photos of the evening. It can be found at: http://bit.ly/2Apad0C. A recording of the panel is posted on the ESD Alliance website, along with additional photos, at: http://bit.ly/2jc5ffQ.

Partition your Design for FPGA Prototyping
December 11, 2017  by Henry Chan

Modern ASIC and SoC designs have increased in complexity such that multiple FPGAs of the largest capacity are now required to prototype the entire functionality of the design. As design sizes increase, more and more FPGAs are required. The capacity and pin limitations of FPGAs create constraints for how the ASIC/SoC design can be mapped into the FPGAs. Aldec’s HES-DVM’s prototyping mode accounts for the limitations of the target FPGAs and allows the user to map a design to the FPGAs within these constraints.

Partitioning a design to fit into multiple FPGAs can be a lot of work

Designing the partitions with HES-DVM is as easy as selecting specific VHDL/SystemVerilog design modules from the hierarchy and moving them to a desired partition. All information about the design modules and the amount of LUTs, Flip-flops, memory blocks, DSP slices, and I/O consumed are displayed for convenience. These values can also be viewed as a percentage of the target FPGAs’ available resources allowing you to know when an FPGA is full.

Adding a module to a partition

Mapping a partition to an FPGA

Once the partitions are finalized, each partition can be assigned to a specific FPGA. A design successfully fitting into the FPGAs on the target prototyping board is only the beginning. There still remains a big problem with the sheer number of connections between the partitions. Modern designs have thousands of internal signals interconnecting major blocks or sub-systems. It’s likely that there won’t be a sufficient amount of direct connections between FPGAs to support the design’s internal wiring. How can the large amount of internal design signals possibly be accommodated by the relatively smaller amount of I/O available from the FPGAs?

For the rest of this article, visit the Aldec Design and Verification Blog.

DownStream: Solutions for Post Processing PCB Designs


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