EDACafe Weekly Review February 28th, 2017

Photos from the Phil Kaufman Award Ceremony and Dinner, A Night to Remember
February 24, 2017  by Bob Smith, Executive Director

The Super Bowl wasn’t the only festive event over the last few weeks! The Electronic Systems Design ecosystem honored Andrzej Strojwas as the 2016 Phil Kaufman Award recipient during an awards ceremony and dinner attended by close to 200 of us from the industry. It was held Thursday, January 26, at the Fourth Street Summit Center in San Jose, Calif.

Caption: Kaufman Award recipient Andrzej Strojwas (standing in the middle with his statuette), along with his extended family, PDF Solutions and Carnegie Mellon colleagues and graduate students.

For those of you who don’t know Dr. Strojwas, he is PDF Solutions’ chief technologist as well as the Keithley professor of Electrical and Computer Engineering at Carnegie Mellon University. He was recognized with the award for his pioneering research in the area of DFM in the semiconductor industry.

The Kaufman Award is presented annually by the ESD Alliance and the IEEE Council on Electronic Design Automation (CEDA). For more information, check out: http://bit.ly/2l95wTO

As I did with the RISC-V event, I won’t try to recapture the evening when two of our favorite chroniclers Peggy Aycinena and Paul McLellan covered the evening so masterfully and neatly depicted the mood. (See the links to their blog posts below.) Instead, I’ll offer you a look at who was there through photos taken by the Alliance’s Paul Cohen and Julie Rogers and ace photographer Ross Mehan of Ross Mehan Photography. The video, produced by Andrew Mellows Video, will be available on the ESD Alliance website shortly.

Qualcomm’s Lu Dai: Energetic leadership for Accellera
February 23, 2017  by Peggy Aycinena

 


Accellera has just announced that Lu Dai, 
Senior Director of Engineering at Qualcomm, is the new chair of the organization.

Although Intel’s Shishpal Rawat, recently retired from Intel, is a hard act to follow as Accellera Chair given his long, productive years leading the organization, if anyone can do it Lu Dai can. He’s enthusiastic, energetic, optimistic, and an engineer – and not necessarily in that order.

Before talking about Accellera in our phone call this week, Dai spoke about DVCon, anchor tenant of Accellera’s outreach to design and verification engineers around the world. This next week, the Silicon Valley version will unfold in San Jose, with DVCon India happening in September, DVCon Europe in October, and the first-ever DVCon China in April.

Oski Technology: new VIP supports Formal Sign-off
February 23, 2017  by Peggy Aycinena


Oski Technology has added a new page to its playbook.
Now it’s not just a services company, it’s an IP company as well. This week, the company announced it’s Formal Verification IP Library targeted at those companies using ARM’s AMBA interface protocols.

When we spoke on the phone about the announcement, I asked Oski VP of Applications Engineering Roger Sabbagh why now for this product release. He said: “I personally have been working in Formal since the year 2000, back when I joined 0-In, and over the years I’ve learned that formal adoption grows slowly.

“Yet although there has never been a knee in the curve, we have seen some important developments in the industry. Synopsys developed PC Formal and Cadence bought Jasper, both indicating that Formal is catching on slowly but surely.”

Portable Stimulus Takes Center Stage At DVCon 2017
February 23, 2017  by Maheen Hamid, co-founder at Breker Verification Systems, Inc

When DVCon opens next week, attendees will hear plenty of talk about Portable Stimulus, a methodology and technology that’s grabbing industry attention and gaining momentum with the design verification community. In fact, I predict it will be the buzz of the conference this year.

ESD Alliance Bulletin: DVCon, New Member Helic, Upcoming Events
February 23, 2017  by Bob Smith, Executive Director

I promised in my last post a special blog post with great photos highlighting the Phil Kaufman Award Ceremony and Dinner January 26. It will go up Monday.

But first, the news that the ESD Alliance will exhibit at DVCon at the DoubleTree Hotel in San Jose, Calif. We’ll be in Booth #100 in the foyer, so please stop by if you’re attending.

During DVCon, we’re co-hosting with OneSpin Solutions a panel, “Ride with the Verify Seven,” moderated by Jim Hogan of Vista Ventures featuring six verification leaders who grew their companies from startup to medium-sized industry player. It will be held Monday beginning at 7 p.m., after the Booth Crawl, until 8:30 p.m. Light refreshments and drinks will be served.

Panelists include:

  • Andy Stein, Vice President of North American Sales from Avery Design Systems
  • Adnan Hamid, CEO at Breker Verification Systems
  • Phil Moorby, Chief Architect of Montana, a Phil Kaufman Award recipient presented to him by the ESD Alliance and IEEE CEDA for inventing the Verilog language
  • Raik Brinkmann, President and CEO of OneSpin, an ESD Alliance Member Company
  • Prakash Narain, President and CEO at Real Intent, an ESD Alliance Member Company
  • Rick Carlson, ESD Alliance Member Company Verific’s Vice President of Sales and advisor to seven early-stage startups

The event is open free of charge to all Alliance member companies and DVCon attendees. Non-members of the Alliance or anyone without a DVCon badge are invited to attend for a fee of $40. Registration information and more details on the event can be found at: http://bit.ly/2kNWx6T

TrueCircuits: IOTPLL


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