EDACafe Weekly Review August 25th, 2016

Real Intent: A sustained culture of Respect & Innovation
August 25, 2016  by Peggy Aycinena

 


Real Intent, a Silicon Valley-based EDA company
, has been underway since 1999. That’s a lot of time for a company to continue to succeed amidst the shifting sands of an industry that specializes in either acquiring smaller companies or under-cutting their prices until the smaller companies simply close their doors.

In other words, Real Intent is a survivor and tells a remarkable story of steady perseverance and a well-established, respectful relationship with its customer base. Without both of these things, the company could not have remained viable.

This week, I enjoyed an excellent phone call with company CEO, Prakash Narain, a conversation of particular interest because Dr. Narain spoke candidly of the challenges that face small EDA companies in the current business climate.

IoT: The Second Coming
August 25, 2016  by Peggy Aycinena

 


This week’s blog post is authored by Bill Finch, Senior VP at CAST, Inc.
, long-time provider of IP cores and platform IP products. The discussion below maps the evolution of technologies and strategies that produced today’s IoT to the critical road map needed to achieve tomorrow’s.


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IoT: The Second Coming

The second wave of the IoT is about to start. In the first wave, there was little clarity about what functionality really mattered. Engineers were tasked with getting products out ASAP. Because of the uncertainty and rush, most first-wave products were built around off-the-shelf parts made by IDMs (Integrated Device Manufacturers). The emphasis was on getting things working, not on optimization.

This will not be true in the second wave.

A Further Preview of DVCon India 2016
August 24, 2016  by Tom Anderson, VP of Marketing

Three weeks ago, we published a post on The Breker Trekker blog that previewed some of the talks and tutorials on the technical program at the upcoming third Design and Verification Conference and Exhibition (DVCon) India on September 15-16 in Bangalore. More of the details on the conference are now available online, and for today we’d like to highlight some of the keynote addresses, panels, and poster sessions on the agenda that also stand out for us.

As always, the program and steering committees have put a lot of thought into keynote speakers who will take a wide view of not just the EDA industry, but the larger electronics industry that we serve. Mentor CEO Wally Rhines is always a great speaker who comes armed with lots of charts and statistics to support his positions. His talk on “Design Verification: Challenging Yesterday, Today and Tomorrow” will survey the history and evolution of verification while predicting some of the future challenges

Much Less Efforting Required
August 24, 2016  by Lauro Rizzatti

EffortingI had a chat with a friend yesterday who announced: “Less efforting is working for me.” The use of the noun effort as a verb –– efforting –– didn’t send me to my online dictionary to check my grammar or linguistic skills. Instead, it took me back 30-odd years to the early days of hardware emulation when efforting could have been the catchphrase.

In those days from the 1980s, the emulator arrived with a crew of applications engineers (AEs in a box, we used to say). Even they didn’t have a magic touch –– it seemingly took forever to tweak the system just so to get it to work. Pricing required some justification efforting as well because they were expense verification tools. As a result, they were reserved for only the largest and most complex chip designs, which, in those days average about 100,000 ASIC gates. Big price tag, big chips, lots of efforting.

Efforting continued into the 1990s as hardware emulation became a bit more popular, though they were an unsightly mess with cables snaking around the boxes, like spaghetti enveloping meatballs, so much so that they were relegated to a back room. With all those cables came in circuit emulation (ICE), the default, actually the only use model to verify the design-under-test (DUT) with real traffic data. While effective, the data in and out of the emulator ran at a lower speed than the actual speed of the real traffic data, requiring the insertion of speed adapters and additional efforting. Further, the manned supervision commanded by the ICE mode limited hardware emulation’s ability to become a shared remote resource.

DownStream: Solutions for Post Processing PCB Designs


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