EDACafe Weekly Review January 19th, 2018

#DAC55 3: Last Call for Designer and IP Track presentations for 2018 event in San Francisco
January 19, 2018  by Sharon Hu - General Chair DAC55 and a professor in dept of CS and Engineering at Univ of Nortre Dame, Indiana

One of the most popular part of Design Automation Conference needs you! The Designer and IP tracks are open for submissions and you have until Jan. 23 to send in your abstracts.

These sessions are where industry experts discuss different tools, flows, and methodologies that will help you and your design team. In addition, they provide excellent opportunities for education and networking between end users and tool developers.

I’ve been to many of these sessions in recent years, and if attendance is any indication, they’ve become valuable parts of the DAC program. Mac McNamara, my predecessor as General Chair last year, compared design to putting socks on a chicken, but I can say from sitting in on several sessions that it can be done!

The Designer and IP track presentations are intended to be free of marketing and sales pitches and tuned to the needs of today’s designers. That’s a key reason they’ve become so popular. Not only will your work receive a lot of attention from fellow designers and tool users but the submission process is extremely easy.

All you need to do to is to submit a 100-word description of your presentation with six slides. Yes, you did read correctly – six slides and 100 words.  If it’s accepted you can begin to educate the 2018 attendees how to put socks on those chickens!

This year’s Designer Track and IP Track will include presentations, poster sessions and a rich set of invited talks/panels for information exchange and interactions.

The DAC Designer Track brings together IC designers, embedded software and system developers, automotive electronics engineers, security experts, engineering managers, and verification engineers from across the globe. Past presenters have included AMD, ARM, Bosch, BMW, Cadence, Delphi, GM, and more.

Leading the Designer track committee is Chair Zhuo Li from Cadence. Zhuo has been a member of the DAC Executive Committee for several years and has experience in leading the Designer Track program.  Zhuo is joined by designer track Vice Chairs Robert Oshana from Qualcomm/NXP and Renu Mehra from Synopsys. Rounding out the excellent team are subcommittee chairs that come from companies such as Global Foundries, AMD, Intel, NXP and Analog Devices. A complete list can be found here.

The IP track this year is chaired by Ty Garbere, here in the Silicon Valley. Ty is new to the Executive Committee but not new to IP.  Ty and his team stretches from the Austin, Texas, to the Bay Area to Marseille, France (see all the names and affiliations here).

 

As part of our outreach to attendees for these tracks, we like to say there is no better way to improve your “Design and IP IQ” in such a short amount of time. To help improve that IQ, submit your proposed presentations today! And remember to visit the dac.com for updates as we head into the final months of planning for 2018.

 

The Phil Kaufman Award Ceremony and Dinner –– Come See and Be Seen!
January 19, 2018  by Bob Smith, Executive Director

Anyone who joins us for the Phil Kaufman Award ceremony and dinner knows attendees are the “who’s who” of the electronic system design ecosystem and this year’s evening will be no different. Come to “see and be seen” at The GlassHouse in San Jose, Calif., Thursday, February 8, for the Phil Kaufman Award ceremony and dinner. We will honor Dr. Rob A. Rutenbar, senior vice chancellor for Research at the University of Pittsburgh, the recipient of the 2017 Phil Kaufman Award for Distinguished Contributions to Electronic System Design.

If you attend, you’ll rub shoulders with executives from Arm, Cadence, Mentor, a Siemens Business, PDF Solutions, Synopsys and ACM SigDA who are sponsoring the evening presented by the ESD Alliance and the IEEE Council on EDA (CEDA). Attendance is open to member companies at a substantial discount. Of course, you don’t need to be a member to attend. Registration is open and information can be found at: http://bit.ly/2mt9XId

Everyone attending the dinner will help us celebrate the positive news coming from our most recent Market Statistics Service (MSS) report. As just noted in our Q3 2017 MSS report, industry revenue was up 8 percent over Q3 2016. Another positive sign –– employment in the system design ecosystem is up almost 10% when compared to Q3 2016.

The MSS newsletter can be found at: https://goo.gl/qd5bvF. Naturally, the complete quarterly MSS report has much more information, containing detailed revenue data broken out by both categories and geographic regions. The report is available to member companies of the ESD Alliance, another excellent reason to join.

About Dr. Rob Rutenbar

Rob Rutenbar’s contributions are significant and include founding multiple startups, including Neolinear, an analog tool company now part of Cadence. As an academic researcher at CMU, he pioneered a range of models, algorithms and tools for analog IC designs. During his tenure at the University of Illinois, he reworked his long-running CMU course, “VLSI CAD: Logic to Layout,” into the first Massive, Open, Online Course (MOOC) on EDA, providing training to thousands of engineers.

He’s a credit to the industry and is well deserving of the Phil Kaufman Award. Please join us in feting Dr. Rob Rutenbar. Everyone at the ESD Alliance and IEEE CEDA looks forward to seeing you February 8. Registration is open until Friday, January 26. Details are available at: http://bit.ly/2mt9XId

Follow us at:

Website: www.esd-alliance.org

ESD Alliance Bridging the Frontier blog: http://bit.ly/2oJUVzl

Twitter: @ESDAlliance

LinkedIn: https://www.linkedin.com/groups/8424092

Facebook: https://www.facebook.com/ESDAlliance

Self-Driving Exploration: Past, Present and Future
January 18, 2018  by Sanjay Gangal

NASA’s first launch didn’t reach the moon. In the quest for self-driving cars automakers are aiming for the autonomous moonshot.  Competition is accelerating between major car brands, tech companies and Tesla. What advanced tech is coming to our roads and when?

Listen to the CES Panel held in Las Vegas.

CES Panel: Autonomous Vehicles in the Cities of Tomorrow
January 18, 2018  by Sanjay Gangal

Where do autonomous vehicles stand today and when will they be ready?  How will they operate in connected cities and will consumers be ready to use them? Listen to this panel of experts working on autonomy share their perspectives on the current and future state of self-driving technology.

Qualcomm President Cristiano Amon is at CES to showcase the company’s latest inventions that are leading the world to 5G in industries from IoT to automotive.

Watch a replay of NVIDIA CEO Jensen Huang’s press event at CES 2018 in Las Vegas, where he unveiled new gaming technology, including Max-Q designed thin and light gaming laptops and new big format gaming displays (or BFGDs), along with a slew of auto news, including NVIDIA DRIVE Xavier processor, DRIVE IX and DRIVE AR as well as partnerships with Volkswagen, Uber, Baidu, ZF and Aurora.

RTOS memory footprint
January 15, 2018  by Colin Walls

Most of the time, I subscribe to the view that “the only stupid question is the one you did not ask”. However, I do have trouble with a question that I have been asked countless times at trade-shows, seminars etc. The question is “How much memory does Nucleus RTOS need?”

It is not that this is a stupid question. It is very sensible to be fully aware of resource utilization with deeply embedded systems. The problem is that I am rarely sure how to give a meaningful and useful answer, so I resort to generalities and this is often viewed with suspicion. The reason for this is that the answer is dependent upon a great many variables …

DownStream: Solutions for Post Processing PCB Designs


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