EDACafe Weekly Review March 29th, 2017

Recap: Decoding Formal Club, Spring 2017
March 29, 2017  by Roger Sabbagh - VP of Applications Engineering at Oski

What better way to celebrate the arrival of spring than another meeting of the Decoding Formal Club! The Decoding Formal Club is a forum for formal verification enthusiasts, pioneers, leaders and friends who work to promote the sharing of ideas, advancement of formal verification technology, and adoption of formal sign-off methodology within the industry. On Tuesday, March 21, the club met to hear presentations from Oski, Nvidia and Arteris.

Vigyan Singhal, Oski CEO and formal verification visionary, started us off by introducing the concept of architectural formal verification. Some system level requirements are, by their very nature, well suited for formal verification. Cache coherence, absence of deadlocks and security features are examples of things that we would want to verify with formal. However, the complexity of today’s systems makes it impractical to do so at the RTL level. Instead, Vigyan talked about how Oski uses abstract components to build a system-level model that can be successfully analyzed by formal verification.

Many in attendance liked this approach but also noted the challenge of ensuring that the behavior of the abstract components matches the implementation in RTL. Vigyan explained how Oski’s methodology has that covered when the properties of the abstract models are validated against the RTL designs to close the loop.

 

Siddartha Papineni, Nvidia

Next Week’s CEO Outlook to Gaze at the Future, Bask in Industry’s Vitality
March 28, 2017  by Bob Smith, Executive Director

The spectacular news this week from the ESD Alliance’s Market Statistics Service (MSS) that revenue increased 18.9 percent for Q4 2016 will be an exclamation point to next week’s CEO Outlook.

For example, revenue for Q4 in all four geographic regions –– Americas, Europe, Middle East and Africa, and Japan and Asia/Pacific –– increased 18.9 percent for Q4 2016 to $2455 million, compared to $2064.5 million in Q4 2015. All product categories saw fourth-quarter growth. In fact, CAE, Semiconductor IP, IC Physical Design & Verification and PCB/MCM reported double-digit increases. Another positive sign is employment is up 6.6% overall.

 

CEO Outlook attendees can expect to hear much more about industry opportunities for growth and challenges as Ed Sperling, editor-in-chief of Semiconductor Engineering, moderates the panel of four of our most visible CEOs and Alliance Board Members. They are: Aart de Geus, CEO at Synopsys, Lip-Bu Tan, president and CEO of Cadence, ARM’s CEO Simon Segars and Wally Rhines, chairman and CEO of Mentor Graphics and board sponsor for the MSS.

The CEO Outlook will be held Thursday, April 6, from 6:30 p.m. until 8:45 p.m. at Synopsys in Mountain View, Calif. Each panelist will offer an opening statement about the future of the industry, share their views on industry trends (including the latest revenue increase), and identify potential opportunities and challenges. Attendees will have a chance to ask questions during an interactive audience-driven Q&A session.

The evening is open free of charge to all ESD Alliance member companies. A private reception for ESD Alliance members only to network with speakers will begin at 5:30 p.m. Non-members are invited to attend for a fee of $25. Dinner and drinks will be provided. More details and registration information can be found at: http://bit.ly/2ocTWFS. Please register today because seating is limited.
The complete quarterly MSS report, containing detailed revenue information broken out by both categories and geographic regions, is available to ESD Alliance members only and considered an invaluable resource. However, a news release with an overview of revenue by product category and region is available at: http://bit.ly/2mNlTXJ

 


Something historic and poignant
is taking place on Thursday, April 6th, that should be of interest to absolutely everyone in the EDA and IP communities. The four most powerful men in these two industries will be on stage for an ESD Alliance panel discussion led by Semiconductor Engineering’s Ed Sperling.

The four panelists include Synopsys Chairman & CEO Aart de Geus, Cadence President & CEO Lip-Bu Tan, Mentor Graphics Chairman & CEO Wally Rhines, and ARM CEO Simon Segars.

The April 6th event will be historic because these Big Four unequivocally define EDA and IP – just as Stanford, Huntington, Hopkins, and Crocker defined Railroads in the West – and it’ll be poignant because you’ll never see them together again. Too many changes ahead.

Of course, the ESDA panel will also be whimsical: You’ll know no more about these CEOs and their companies at the end of the evening than you knew when you first arrived. That doesn’t mean the evening won’t be entertaining.

DownStream: Solutions for Post Processing PCB Designs
S2C: FPGA Base prototyping- Download white paper


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