EDACafe Weekly Review May 12th, 2016

 


IP will be well represented at DAC
 according to Adapt IP Michael “Mac” McNamara, and he should know. He’s helped build the IP Track at the show and is concerned that everyone understand the IP-related content in Austin this year will be deep and wide.

Mac and I spoke by phone recently. He’d read a blog a posted here in April expressing skepticism about IP coverage at DAC. Therein, I suggested the content set for Austin in June was inadequate, given the important role IP plays in chip design today.

A thoughtful McNamara wanted to respond to this critique; he wanted to evangelize for the quality of the content at DAC – particularly as he is Vice Chair of the conference this year and will be General Chair in 2017. [Cadence’s Chuck Alpert is General Chair here in 2016.]

Silexica: Holy Grail for Multi-core
May 12, 2016  by Peggy Aycinena

 


Aachen-based Silexica is making waves in the world of multi-core and embedded systems
, as evidenced by their recent win in the German Silicon Valley Accelerator program. Company leadership was motivated to spend Q1_2016 in Silicon Valley, networking and meeting with thought leaders in the Bay Area’s tech community.

While he was in California, I had a chance to speak by phone Silexica CEO Max Odendahl. As many know, the problem of parsing code to take advantage of multi-core systems is a massively tough one to solve, one of the Grand Challenges in computing. My conversation with Odendahl was compelling, because it would appear his company has the solution.

SoCs in Space!
May 11, 2016  by Tom Anderson, VP of Marketing

The title of last week’s post was a play on a Mark Twain quote. This week I draw from a more contemporary source: The Muppets. Some episodes of the legendary family TV show featured a skit called “Pigs in Space.” In my head I’m reading “SoCs in Space!” with the same booming intonation used on the show for “Pigs in Space” to lead into a somewhat more serious discussion about the use of advanced chips in extreme conditions.

My prompt for this particular post came not from TV, but from an announcement yesterday that VORAGO Technologies is offering an ARM-based microcontroller (MCU) “designed specifically for radiation and extreme temperature operation without up-screening.” In other words, they ship an MCU that’s ready to use in such traditionally challenging environments as automobiles and industrial controllers as well as, yes, space. That got me thinking about even more complex chips such as SoCs and the extreme conditions they might have to face.

Aldec Verification Tools Implement the ASIC Verification Flow
May 10, 2016  by Dr. Stanley M. Hyduke

Aldec-Verification-SpectrumAldec has, over the last 30 years, established itself as the preferred provider of high-performance, cost-effective verification tools for use in proving out complex FPGA designs. As the logic capacity and capability of FPGAs have increased, however, the distinction between FPGA and ASIC design has narrowed. A modern FPGA verification flow looks very much like an ASIC verification flow.

Small and large fabless companies alike need a reliable verification partner that suits their budgets while still providing a high level of support. To answer the call, we at Aldec have extended our spectrum of verification tools for use in digital ASIC designs.

A Basic ASIC Verification Flow

Managing verification for ASICs requires a well-defined verification plan.  Efficient verification planning starts with functional and design requirements in which requirements are mapped to verification methods, scenarios, goals and metrics, coverage groups, and results. Mapping entails traceability throughout the project that must be well maintained so that changes in the requirements will seamlessly reflect potential changes downstream to the elements of the verification plan.

While traceability can benefit any design, it is mandatory for safety-critical designs regulated by standards such as ISO-26262 for automotive, IEC-61508 for industrial and DO-254 for avionics.

What’s Really Needed for FinFET Layout (Part 1)
May 10, 2016  by Graham Etchells, Director of Product Marketing at Synopsys

Over the last series of blogs we have looked at which tools the layout engineer has available to him/her to help deal with the complexity of doing layout with FinFETs. Even though there are tools that help, the fact is there is still a productivity hit when comparing the time it takes to do a FinFET-based layout vs. a planar CMOS layout. When I asked my layout colleagues “How much longer does it take to do a FinFET-based design vs. planar CMOS?”, they said it takes 2-3X longer.

So, if we are to recoup layout productivity when doing a FinFET-based design, which areas should we focus on? Well, let’s start at the very beginning, which, according to Julie Andrews in The Sound of Music, is a very good place to start. The task of generating the devices and placing them such that they meet all the design rules and will produce a robust working design is about 30% of the layout time. So if we can speed up this task then we will gain back some of the productivity we lost due to the complexity of the FinFET process.

Real Intent Job


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