EDACafe Weekly Review December 9th, 2016

Registration Opens for Phil Kaufman Award Dinner, More News from the ESD Alliance
December 9, 2016  by Bob Smith, Executive Director

Registration opened this week for the Phil Kaufman Award Presentation and Dinner to honor Andrzej Strojwas, chief technologist at PDF Solutions and Keithley professor of Electrical and Computer Engineering at Carnegie Mellon University. AndrzejTrophyGraphic

I hope you’ll join us for a celebration that helps us kicks off 2017. The dinner will be held Thursday, January 26, at the Fourth Street Summit Center in San Jose, Calif., where we held the dinner paying tribute to Mentor Graphics’ Wally Rhines in 2015. The evening will begin with a reception and cocktails at 6:30 p.m. The dinner and award presentation will be run from 7:30 p.m. until 9 p.m. We have special entertainment planned that will challenge your senses!

Andrzej is being recognized with the award, presented annually by the ESD Alliance and the IEEE Council on Electronic Design Automation (CEDA), for his pioneering research in the area of design for manufacturing (DFM) in the semiconductor industry.

Reservations are $175 per person for ESD Alliance and IEEE members or $250 per person for non-members. Seating is limited and we can accept R.S.V.P.s until Thursday, January 12. To reserve your seat at the 2016 Phil Kaufman Award Presentation and Dinner, visit our online registration.

Tables of 10 are available if your company be interested in sponsoring the event. Sponsorships will heighten a company’s visibility and brand exposure through positive publicity and promotion, and through signage and the program at the event. By sponsoring the dinner, your company is showing the community that it believes in the vibrancy of our industry and honoring those individuals who created it.

To find out more, visit our sponsorship page or call (408) 287-3322.

More information on the venue:

Fourth Street Summit Center

7th Floor (top floor)

88 South 4th Street

San Jose, Calif.

Parking couldn’t be easier. The Fourth Street Summit Center is at the top of a seven-story parking garage –– the Fourth Street Garage. Park your car and take the elevator up to the event.

Save the Date: Open Source and RISC-V Discussion January 18

Also in January will be a discussion about Open Source and the RISC-V processor hosted by Jim Hogan of Vista Ventures. Jim’s guests will be Rick O’Connor, executive director of the RISC-V Foundation, and Yunsup Lee, SiFive’s chief technology officer. It will be held Wednesday, January 18, from 6-8:30 p.m. at Cadence in San Jose, Calif. I’ll share the details next week.

The ESD Alliance Annual Membership meeting will precede this event at 5 p.m. Alliance Members will receive a separate notice with more information shortly.

Multi-Die IC Design Guide

Here’s a reminder that we are about to begin editing and compiling the next edition of the popular and comprehensive Multi-Die IC Design Guide, a yearly collection of information about multi-die IC design. The 500-page guide includes background information on technologies, trends, definitions and real-world examples. It will have a section with supplier content and technical papers on multi-die solutions that ranges from design –– automation, analysis and modeling solutions –– to manufacturing with specifics on packaging and manufacturing solutions.

The current edition introduced at DAC 2016 has been downloaded by more than 300 people all over the world from a diverse array of companies including many at the Fortune 100. It is available as a free download.

ESD Alliance Memberships Available

And one more reminder: If your company would like to join the ESD Alliance or learn more about joining in 2017, please check out our latest newsletter or visit the ESD Alliance website to read about our committees and ongoing initiatives. I’m available to answer questions as well and can be contacted at bob@esd-alliance.org.

Constrain Me, Please
December 8, 2016  by Adnan Hamid, CEO of Breker

In the movies, when a person acts irrationally they are usually declared to be mad and quickly placed in a straitjacket for the protection of themselves and those around them. If we continue those thoughts into the world of verification, SystemVerilog must be declared to be a mad language.

CST Webinar Series
TrueCircuits: IOTPLL


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