A showcase for electronic design videos around the world-wide web.
February 6th, 2012 by Sanjay Gangal
DC Drop Analysis is a crucial step in any PCB design flow. Learn how utilizing DC Drop Analysis can greatly enhance your ability to identify potential power issues. Explore how co-simulating DC Drop and Thermal Analyses can optimize your entire power delivery network.
Presented by Steve McKinney of Mentor Graphics
February 3rd, 2012 by Sanjay Gangal
A demonstration of how Schematic Driven Layout (SDL) is used in Tanner’s L-Edit using HiPer DevGen for analog layout acceleration.
February 2nd, 2012 by Sanjay Gangal
Rajeev Madhavan, Magma CEO, describes how Magma’s Silicon One initiative provides advanced digital implementation, analog/mixed-signal design, timing analysis, circuit simulation and yield management technology solutions that allow semiconductor companies to develop differentiated and profitable SoCs, ASICs, memory devices, analog designs and high-performance cores.
February 1st, 2012 by Sanjay Gangal
Mar Hershenson, Vice President, Product Development, Custom Design Business Unit at Magma, provides an overview of Titan and how it allows analog designers to more fully explore the design space to significantly improve performance and dramatically reduce power consumption on both new and existing analog designs.
January 30th, 2012 by Sanjay Gangal
This is a demonstration of using current mirrors in Tanner EDA’s HiPer DevGen analog layout acceleration tool.
January 27th, 2012 by Sanjay Gangal
Josefina Hobbs, Technical Solutions Architect for the Synopsys Eclypse Low Power Solution, describes the various special cells that can be used in UPF-enabled advanced low power design.
January 26th, 2012 by Sanjay Gangal
Eric Huang demonstrates USB 3.0 interoperability with a USB 3.0 Certification Gold Tree including all USB traffic types.
Cool Things You Can Do With the Discovery Visualization Environment (DVE) — Searching And Cool GUI Tips
January 25th, 2012 by Sanjay Gangal
Verification expert Yaron Ilani explains how to easily search for signals or scopes in the Discovery Visualization Environment (DVE) and gives some great GUI tricks.
January 24th, 2012 by Sanjay Gangal
Utilizing the LeCroy’s protocol analyzer, exerciser and test suite, Synopsys demonstrates PCI Express 3.0 transactions through the DesignWare PCI Express 3.0 IP implemented on the Synopsys HAPS FPGA prototyping system. Presented by Scott Knowlton and Torrey Lewis.
January 23rd, 2012 by Sanjay Gangal
Synopsys demonstrates the DesignWare SATA 6 Gb/s AHCI host controller and PHY implemented on Synopsys’ HAPS FPGA-Based Prototyping system interoperating with a commercially available SATA 6 Gb/s device. Presented by Scott Knowlton and Mat Loikkanen.