A showcase for electronic design videos around the world-wide web.
January 30th, 2012 by Sanjay Gangal
This is a demonstration of using current mirrors in Tanner EDA’s HiPer DevGen analog layout acceleration tool.
January 27th, 2012 by Sanjay Gangal
Josefina Hobbs, Technical Solutions Architect for the Synopsys Eclypse Low Power Solution, describes the various special cells that can be used in UPF-enabled advanced low power design.
January 26th, 2012 by Sanjay Gangal
Eric Huang demonstrates USB 3.0 interoperability with a USB 3.0 Certification Gold Tree including all USB traffic types.
Cool Things You Can Do With the Discovery Visualization Environment (DVE) — Searching And Cool GUI Tips
January 25th, 2012 by Sanjay Gangal
Verification expert Yaron Ilani explains how to easily search for signals or scopes in the Discovery Visualization Environment (DVE) and gives some great GUI tricks.
January 24th, 2012 by Sanjay Gangal
Utilizing the LeCroy’s protocol analyzer, exerciser and test suite, Synopsys demonstrates PCI Express 3.0 transactions through the DesignWare PCI Express 3.0 IP implemented on the Synopsys HAPS FPGA prototyping system. Presented by Scott Knowlton and Torrey Lewis.
January 23rd, 2012 by Sanjay Gangal
Synopsys demonstrates the DesignWare SATA 6 Gb/s AHCI host controller and PHY implemented on Synopsys’ HAPS FPGA-Based Prototyping system interoperating with a commercially available SATA 6 Gb/s device. Presented by Scott Knowlton and Mat Loikkanen.
January 20th, 2012 by Sanjay Gangal
Synopsys verification expert Yaron Ilani explains how to debug UVM sequences and transactions in the Discovery Visualization Environment (DVE).
January 17th, 2012 by Sanjay Gangal
An in-depth technical discussion and demonstration on how the three key elements of Silicon Realization—-intent, abstraction, and convergence—can be applied to mixed-signal challenges and deliver an end-to-end, predictable path to silicon success. Key concepts include analog behavioral modeling, design (power) intent for mixed-signal IP, analog/digital interoperability, and mixed-signal design closure.
Presented at CDNLive! 2010 by Dave Desharnais, Product Marketing Group Director, Silicon Realization, Cadence
January 13th, 2012 by Sanjay Gangal
Productivity and predictability issues are making it crucial for engineers to optimize functional, electrical, and physical specifications concurrently rather than in the typical EDA silos. This close look into Silicon Realization reveals three critical requirements: unified design and verification intent; higher levels of abstraction; and convergence of late-stage design/manufacturing data into the early phases of design.
Presented at CDNLive! 2010 by Chi-Ping Hsu, Ph.D, Senior Vice President, Research and Development, Silicon Realization Group, Cadence
December 9th, 2011 by Sanjay Gangal