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 Video Roundup
Sanjay Gangal
Sanjay Gangal
A showcase for electronic design videos around the world-wide web.

DesignCon 2012: New HyperLynx Release 8.2 with Thermal / Power Co-simulation Analysis

February 13th, 2012 by Sanjay Gangal

Steven McKinney from Mentor Graphics gave an update on the new HyperLynx Release 8.2 with thermal / power co-simulation analysis at DesignCon 2012.

Steven is a business development manager for Mentor Graphic’s Board System Division where he supports Mentor’s PCB analysis technologies which include tools for Signal Integrity, Power Integrity, Thermal and EMC design. Steven has previously held roles in technical marketing at Mentor Graphics, specializing in signal integrity and EMC analysis tools and educating the engineering community on signal integrity, power integrity, and EMC design issues. Prior to working for Mentor, Steven was a signal integrity engineer at Dell Computer developing server hardware. Steven received his BSEE and MSEE from North Carolina State University.

Calibre InRoute: Signoff Metal Fill Insertion, CMP Impact and Olympus Timing Analysis

February 10th, 2012 by Sanjay Gangal

This presentation is by Benny Winefeld, Product Engineering Manager, Place and Route Division at Mentor Graphics.    By using Calibre InRoute, the effects of metal fill insertion and CMP on routing and signal timing can be analyzed for a physical design from within the Olympus environment.

Calibre InRoute – Signoff Litho (LFD) Analysis and Automated Repair

February 9th, 2012 by Sanjay Gangal

This presentation is by Benny Winefeld, Product Engineering Manager, Place and Route Division at Mentor Graphics.    By using Calibre InRoute, sign-off lithography (LFD) analysis and automatic repair can be done for a physical design from within the Olympus environment.

Manufacturing Closure for Advanced Node Designs within Place and Route

February 8th, 2012 by Sanjay Gangal

Mentor Graphics developed Calibre InRoute to support manufacturing closure for advanced node designs by bringing Calibre signoff capabilities into the place and route environment.

This short video provides an overview of the Calibre InRoute solution.

Computational Lithography Solutions for 22nm and Beyond

February 7th, 2012 by Sanjay Gangal

Mentor Graphics is committed to being the leader in computational lithography solutions for 22nm and beyond.  This video presentation discusses the challenges and necessary solutions for IC success.

Tutorial: Better PCB Power Design with DC Drop Analysis

February 6th, 2012 by Sanjay Gangal

DC Drop Analysis is a crucial step in any PCB design flow. Learn how utilizing DC Drop Analysis can greatly enhance your ability to identify potential power issues. Explore how co-simulating DC Drop and Thermal Analyses can optimize your entire power delivery network.

Presented by Steve McKinney of Mentor Graphics

Accelerating Schematic Driven Layout of Analog ICs

February 3rd, 2012 by Sanjay Gangal

A demonstration of how Schematic Driven Layout (SDL) is used in Tanner’s L-Edit using HiPer DevGen for analog layout acceleration.

Creating Differentiated Technology in Silicon

February 2nd, 2012 by Sanjay Gangal

Rajeev Madhavan, Magma CEO,  describes how Magma’s Silicon One initiative provides advanced digital implementation, analog/mixed-signal design, timing analysis, circuit simulation and yield management technology solutions that allow semiconductor companies to develop differentiated and profitable SoCs, ASICs, memory devices, analog designs and high-performance cores.

Accelerating Mixed-Signal Design for Low Power using Titan

February 1st, 2012 by Sanjay Gangal

Mar Hershenson, Vice President, Product Development, Custom Design Business Unit at Magma, provides an overview of Titan and how it allows analog designers to more fully explore the design space to significantly improve performance and dramatically reduce power consumption on both new and existing analog designs.

Accelerating Analog IC Layout with Current Mirrors

January 30th, 2012 by Sanjay Gangal

This is a demonstration of using current mirrors in Tanner EDA’s HiPer DevGen analog layout acceleration tool.

S2C: FPGA Base prototyping- Download white paper

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