Video Roundup

Sanjay Gangal
Sanjay Gangal
A showcase for electronic design videos around the world-wide web.

Optimizing Parmeterized EM Shapes in AWR’s AXIEM 3D Planar Analysis Tool

 
March 30th, 2012 by Sanjay Gangal

Dr. Jaakko Juntunen, Head of EM Applications for AWR Europe present on the optimization of parameterized EM shapes in the AXIEM 2011 3D planar analysis design tool.

Thermal Simulation of Power Amplifier with SYMMIC and Microwave Office

 
March 26th, 2012 by Sanjay Gangal

John Fiela from CapeSym presents integration of SYMMIC thermal simulation software with Microwave Office from AWR.   AWR’s Microwave Office high-frequency design platform and CapeSym’s easy-to-use SYMMIC templates produce unique and unparalleled electrical-thermal MMIC co-design of high-power RF components.

Inside IBM EDA: 50 Years of Innovation

 
March 22nd, 2012 by Sanjay Gangal

IBM has a long history of innovation in the field on electronic design automation (EDA), beginning in the 1950′s when IBM started mass-producing computers. Engineers saw the need to control and streamline production and began using early computers such as the IBM 704 to document designs and to check the correctness of the Boolean equations specifying the behavior. In the decades that followed, IBM continued facing new challenges and solving them with pioneering inventions including circuit simulation, static timing analysis, Boolean comparison, cycle simulation, hardware acceleration, logic and physical synthesis, large scale physical design, layout checking and automated testing in manufacturing.

This video, Inside IBM EDA: 50 Years of Innovation, describes some of the innovations developed at IBM through a series of interviews with a few of the original pioneers. A small team of volunteers from IBM’s EDA community created this video for an internal workshop. They are now making it available for a larger audience.

Integration of AWR’s Visual System Simulator with National Instrument’s Labview

 
March 19th, 2012 by Sanjay Gangal

This video presentation covers the integration of AWR’s Visual System Simulator with National Instrument’s Labview and is presented by Gent Paparisto.

Gent Paparisto, Ph.D., is a Senior Systems Engineer at AWR. He received his Ph.D. in electrical engineering from the University of Southern California (USC) and has extensive experience in research, design, development, and implementation of communication systems and algorithms for wireless, satellite, and wireline applications. He has lead and participated in the design and implementation of several products for cellular and wireless systems. Dr. Paparisto has authored a number of publications in international journals and conferences, served on the technical program committees of various IEEE conferences and contributed to the 3GPP GERAN standardization group.

Tutorial: Partitioning Power Domains

 
March 6th, 2012 by Sanjay Gangal

Josefina Hobbs, Technical Solutions Architect for the Synopsys Eclypse Low Power Solution, defines the concept of a power domain and explains how to properly partition. She also offers guidance on the criteria for deciding whether, and how many, power domains should be used.

Accelerating Analog IC Layout with Differential Pairs

 
February 17th, 2012 by Sanjay Gangal

This is a demonstration of  manipulating differential pairs in Tanner EDA’s HiPer DevGen analog layout acceleration tool.

DesignCon 2012: Joint ANSYS / Apache Interview on Product Roadmap and Integration

 
February 14th, 2012 by Sanjay Gangal

The worldwide need for smart, energy-efficient electronics has never been greater while engineering challenges continually expand. Solutions to these engineering challenges rely on accurate, predictive simulation software.  The acquisition of Apache complements ANSYS’ software solutions by bringing together best-in-class products that drive ANSYS’ system vision for integrated circuits, electronic packages and printed circuit boards.

Aveek Sarkar from Apache and Larry Williams of ANSYS discuss product roadmaps and integration from both companies.

DesignCon 2012: New HyperLynx Release 8.2 with Thermal / Power Co-simulation Analysis

 
February 13th, 2012 by Sanjay Gangal

Steven McKinney from Mentor Graphics gave an update on the new HyperLynx Release 8.2 with thermal / power co-simulation analysis at DesignCon 2012.

Steven is a business development manager for Mentor Graphic’s Board System Division where he supports Mentor’s PCB analysis technologies which include tools for Signal Integrity, Power Integrity, Thermal and EMC design. Steven has previously held roles in technical marketing at Mentor Graphics, specializing in signal integrity and EMC analysis tools and educating the engineering community on signal integrity, power integrity, and EMC design issues. Prior to working for Mentor, Steven was a signal integrity engineer at Dell Computer developing server hardware. Steven received his BSEE and MSEE from North Carolina State University.

Calibre InRoute: Signoff Metal Fill Insertion, CMP Impact and Olympus Timing Analysis

 
February 10th, 2012 by Sanjay Gangal

This presentation is by Benny Winefeld, Product Engineering Manager, Place and Route Division at Mentor Graphics.    By using Calibre InRoute, the effects of metal fill insertion and CMP on routing and signal timing can be analyzed for a physical design from within the Olympus environment.

Calibre InRoute – Signoff Litho (LFD) Analysis and Automated Repair

 
February 9th, 2012 by Sanjay Gangal

This presentation is by Benny Winefeld, Product Engineering Manager, Place and Route Division at Mentor Graphics.    By using Calibre InRoute, sign-off lithography (LFD) analysis and automatic repair can be done for a physical design from within the Olympus environment.

Kilopass
CAD/SW Engineer



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