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Archive for the ‘Synopsys’ Category

Tutorial: Partitioning Power Domains

Tuesday, March 6th, 2012

Josefina Hobbs, Technical Solutions Architect for the Synopsys Eclypse Low Power Solution, defines the concept of a power domain and explains how to properly partition. She also offers guidance on the criteria for deciding whether, and how many, power domains should be used.

Synopsys USB 3.0 Host and PHY Interop with USB Devices of All Speeds

Thursday, January 26th, 2012

Eric Huang demonstrates USB 3.0 interoperability with a USB 3.0 Certification Gold Tree including all USB traffic types.

Cool Things You Can Do With the Discovery Visualization Environment (DVE) — Searching And Cool GUI Tips

Wednesday, January 25th, 2012

Verification expert Yaron Ilani explains how to easily search for signals or scopes in the Discovery Visualization Environment (DVE) and gives some great GUI tricks.

Synopsys DesignWare PCI Express 3.0 with LeCroy Protocol Test Suite

Tuesday, January 24th, 2012

Utilizing the LeCroy’s protocol analyzer, exerciser and test suite, Synopsys demonstrates PCI Express 3.0 transactions through the DesignWare PCI Express 3.0 IP implemented on the Synopsys HAPS FPGA prototyping system.  Presented by Scott Knowlton and Torrey Lewis.

Synopsys DesignWare SATA 6 Gb/s AHCI Host Controller and PHY

Monday, January 23rd, 2012

Synopsys demonstrates the DesignWare SATA 6 Gb/s AHCI host controller and PHY implemented on Synopsys’ HAPS FPGA-Based Prototyping system interoperating with a commercially available SATA 6 Gb/s device. Presented by Scott Knowlton and Mat Loikkanen.


Cool Things You Can Do With the Discovery Visualization Environment (DVE) — Debugging UVM Sequences

Friday, January 20th, 2012

Synopsys verification expert Yaron Ilani explains how to debug UVM sequences and transactions in the Discovery Visualization Environment (DVE).


Tutorial: Rapid Design Exploration with the Lynx Design System

Friday, December 9th, 2011

This 2011 SNUG Boston tutorial shows how to use the Lynx Design System for rapid design exploration and was presented by Kriss Westland of Synopsys.

IDT & BULL Improve Design Efficiency and Schedule Predictability with The Lynx Design System

Friday, December 9th, 2011

At recent Synopsys User’s Group (SNUG) events earlier this year semiconductor companies IDT and BULL shared their experiences on how the Lynx Design System contributed to their project successes:

idt_stacy_frank_video_image.gif “It saves my time so I can focus on more important tasks…At the end of the day, when you are taping out… you can see that all is good .” Stacy Frank,
Staff Design Engineer


S2C: FPGA Base prototyping- Download white paper

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