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Archive for the ‘Analog Mixed-Signal’ Category

Accelerating Analog IC Layout with Differential Pairs

Friday, February 17th, 2012

This is a demonstration of  manipulating differential pairs in Tanner EDA’s HiPer DevGen analog layout acceleration tool.

Accelerating Schematic Driven Layout of Analog ICs

Friday, February 3rd, 2012

A demonstration of how Schematic Driven Layout (SDL) is used in Tanner’s L-Edit using HiPer DevGen for analog layout acceleration.

 

Creating Differentiated Technology in Silicon

Thursday, February 2nd, 2012

Rajeev Madhavan, Magma CEO,  describes how Magma’s Silicon One initiative provides advanced digital implementation, analog/mixed-signal design, timing analysis, circuit simulation and yield management technology solutions that allow semiconductor companies to develop differentiated and profitable SoCs, ASICs, memory devices, analog designs and high-performance cores.

Accelerating Mixed-Signal Design for Low Power using Titan

Wednesday, February 1st, 2012

Mar Hershenson, Vice President, Product Development, Custom Design Business Unit at Magma, provides an overview of Titan and how it allows analog designers to more fully explore the design space to significantly improve performance and dramatically reduce power consumption on both new and existing analog designs.

Accelerating Analog IC Layout with Current Mirrors

Monday, January 30th, 2012

This is a demonstration of using current mirrors in Tanner EDA’s HiPer DevGen analog layout acceleration tool.




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