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Cadence Silicon Realization Overview
January 13th, 2012 by Sanjay Gangal
Productivity and predictability issues are making it crucial for engineers to optimize functional, electrical, and physical specifications concurrently rather than in the typical EDA silos. This close look into Silicon Realization reveals three critical requirements: unified design and verification intent; higher levels of abstraction; and convergence of late-stage design/manufacturing data into the early phases of design.
Watch Cadence Silicon Realization Overview
Presented at CDNLive! 2010 by Chi-Ping Hsu, Ph.D, Senior Vice President, Research and Development, Silicon Realization Group, Cadence
Categories: Cadence, Silicon Realization