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 Video Roundup

Archive for January, 2012

Accelerating Analog IC Layout with Current Mirrors

Monday, January 30th, 2012

This is a demonstration of using current mirrors in Tanner EDA’s HiPer DevGen analog layout acceleration tool.

Tutorial: Power Management Cells in Low Power Design

Friday, January 27th, 2012

Josefina Hobbs, Technical Solutions Architect for the Synopsys Eclypse Low Power Solution, describes the various special cells that can be used in UPF-enabled advanced low power design.

Synopsys USB 3.0 Host and PHY Interop with USB Devices of All Speeds

Thursday, January 26th, 2012

Eric Huang demonstrates USB 3.0 interoperability with a USB 3.0 Certification Gold Tree including all USB traffic types.

Cool Things You Can Do With the Discovery Visualization Environment (DVE) — Searching And Cool GUI Tips

Wednesday, January 25th, 2012

Verification expert Yaron Ilani explains how to easily search for signals or scopes in the Discovery Visualization Environment (DVE) and gives some great GUI tricks.

Synopsys DesignWare PCI Express 3.0 with LeCroy Protocol Test Suite

Tuesday, January 24th, 2012

Utilizing the LeCroy’s protocol analyzer, exerciser and test suite, Synopsys demonstrates PCI Express 3.0 transactions through the DesignWare PCI Express 3.0 IP implemented on the Synopsys HAPS FPGA prototyping system.  Presented by Scott Knowlton and Torrey Lewis.

Synopsys DesignWare SATA 6 Gb/s AHCI Host Controller and PHY

Monday, January 23rd, 2012

Synopsys demonstrates the DesignWare SATA 6 Gb/s AHCI host controller and PHY implemented on Synopsys’ HAPS FPGA-Based Prototyping system interoperating with a commercially available SATA 6 Gb/s device. Presented by Scott Knowlton and Mat Loikkanen.


Cool Things You Can Do With the Discovery Visualization Environment (DVE) — Debugging UVM Sequences

Friday, January 20th, 2012

Synopsys verification expert Yaron Ilani explains how to debug UVM sequences and transactions in the Discovery Visualization Environment (DVE).


Realizing End-to-End Mixed-Signal Design

Tuesday, January 17th, 2012

An in-depth technical discussion and demonstration on how the three key elements of Silicon Realization—-intent, abstraction, and convergence—can be applied to mixed-signal challenges and deliver an end-to-end, predictable path to silicon success. Key concepts include analog behavioral modeling, design (power) intent for mixed-signal IP, analog/digital interoperability, and mixed-signal design closure.

Watch Realizing End-to-End Mixed-Signal Design

Presented at CDNLive! 2010 by Dave Desharnais, Product Marketing Group Director, Silicon Realization, Cadence


Cadence Silicon Realization Overview

Friday, January 13th, 2012

Productivity and predictability issues are making it crucial for engineers to optimize functional, electrical, and physical specifications concurrently rather than in the typical EDA silos. This close look into Silicon Realization reveals three critical requirements: unified design and verification intent; higher levels of abstraction; and convergence of late-stage design/manufacturing data into the early phases of design.

Watch Cadence Silicon Realization Overview

Presented at CDNLive! 2010 by Chi-Ping Hsu, Ph.D, Senior Vice President, Research and Development, Silicon Realization Group, Cadence

S2C: FPGA Base prototyping- Download white paper
TrueCircuits: IoTPLL

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