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Archive for September 5th, 2013

The demise of VHDL has been greatly exaggerated

Thursday, September 5th, 2013

I don’t recall when it was the first time that I heard VHDL was a dying language, but for sure it was many years ago, maybe as far back as the late 1990s. Obviously the EDA futurists of then got it very wrong, and I was recently wondering if I could put a number on how wrong.

At Verific, as the premier provider of SystemVerilog and VHDL parsers to many  EDA, FPGA, and semiconductor companies, we do have some good insights in what our customers license from us and how they use it. Since its start, Verific has shipped just over 100 licenses. So I sat down and tallied the HDL languages companies obtained from Verific during that period. Here is the countdown


S2C: FPGA Base prototyping- Download white paper

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